A 1.1 V 10-bit 62MS/s pipeline ADC with two-step non-overlapping clock generation for multi I-Q channel RF receivers

Abstract

A multi-channel pipeline analog-to-digital converter (ADC) with two-step non-overlapping clock generation is presented. Op-amp sharing and reference buffer sharing between channels are implemented without a front-end sample-and-hold amplifier for low power consumption. The proposed clock generator can easily implement short reset phases between non-overlapping clocks to remove the memory effect from opamp sharing. The prototype 4-channel ADCs are implemented in a 0.11 μm CMOS process. The 10 bit ADC achieve 56.6 dB (9.1 bit ENOB) SNDR and 72.2 dB SFDR with 3 MHz input frequency. Each ADC slice occupies 0.4 mm2 and consumes 13 mW at 62 MS/s sampling frequency under 1.1 V supply.