Power and Area Efficient Pipelined ADC Stage in Digital CMOS Technology

Abstract

ABSTRACTA power and area efficient metal-oxide semiconductor field-effect transistor (MOSFET)-only 1.5-bit fully differential pipelined analog-to-digital converter (ADC) stage is proposed and designed in TSMC 0.18 μm digital CMOS technology with supply voltage of 1.8 V. It is based on charge pump based technique to achieve the stage voltage gain of 2. Various capacitances are implemented by MOSCAPs (capacitance offered by the MOSFET), offering compatibility with cheaper digital complimentary metal-oxide semiconductor (CMOS) process in order to reduce the much required manufacturing cost. The proposed stage suffers from only linear gain error with full signal swing of 2 V peak-to-peak (p–p) differential. Using the proposed stage, un-calibrated signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) for 10-bit, 100 MS/s pipelined ADC are 40.11 and 40.86 dB, respectively, which can be further increased by using a simple digital calibration technique. Comparison between the proposed stage and conventional operational amplifier based stage shows insensitivity towards capacitor mismatch along with power savings and design simplicity.