Abstract
This brief presents a digital background calibration technique for pipelined analog-to-digital converters (ADCs) to correct the capacitor mismatch, finite dc gain, and nonlinearity of residue amplifiers. It estimates the calibration coefficients at start-up by a modified self-measurement method with low-precision stimulation signals in the multistage calibration. Then, during the ADC normal operation, a sliding histogram in the vicinity of the decision boundaries of stage comparators is utilized to adjust the calibration coefficients in order to follow the variation of errors. To do so, the ratio of information achieved from the initial and new histograms is used to update the calibration coefficients. Behavioral simulation results of a 12-bit pipelined ADC show that the proposed calibration technique improves the ADC linearity by more than 4 bits and it is robust against the variation of errors.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: IEEE Transactions on Circuits and Systems II: Express Briefs
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
