pF Capacitive Load Research Articles

An Ultra-Low-Voltage Transconductance Stable and Enhanced OTA for ECG Signal Processing.

In this paper, a rail-to-rail transconductance stable and enhanced ultra-low-voltage operational transconductance amplifier (OTA) is proposed for electrocardiogram (ECG) signal processing. The variation regularity of the bulk transconductance of pMOS and nMOS transistors and the cancellation mechanism of two types of transconductance variations are revealed. On this basis, a transconductance stabilization and enhancement technique is proposed. By using the "current-reused and transconductance-boosted complementary bulk-driven pseudo-differential pairs" structure, the bulk-driven pseudo-differential pair during the input common-mode range (ICMR) is stabilized and enhanced. The proposed OTA based on this technology is simulated using the TSMC 0.18 μm process in a Cadence environment. The proposed OTA consumes a power below 30 nW at a 0.4 V voltage supply with a DC gain of 54.9 dB and a gain-bandwidth product (GBW) of 14.4 kHz under a 15 pF capacitance load. The OTA has a high small signal figure-of-merit (FoM) of 7410 and excellent common-mode voltage (VCM) stability, with a transconductance variation of about 1.35%. Based on a current-scaling version of the proposed OTA, an OTA-C low-pass filter (LPF) for ECG signal processing with VCM stability is built and simulated. With a -3 dB bandwidth of 250 Hz and a power consumption of 20.23 nW, the filter achieves a FoM of 3.41 × 10-13, demonstrating good performance.

A transient-enhanced output-capacitorless LDO regulator with non-inverting pull–push gain stage

A novel non-inverting pull–push gain stage output-capacitorless low-dropout regulator (OCL-LDO) is introduced, designed specifically for power management of system-on-chip (SoC). The incorporation of an innovative non-inverting gain stage (NIGS) serves to shift the non-dominant parasitic poles to higher frequencies, thereby enhancing the overall stability of the system. The proposed pull-push configuration markedly improves the slew rate limitation at the gate of the power transistor. Post-layout simulation outcomes, corroborated through a 180-nm CMOS fabrication process, indicate that the proposed LDO regulator maintains stability across a wide range of loading currents, from 0 mA to 100 mA, with a Miller compensation capacitance of only 3.5 pF. The circuit operates with a quiescent current of 143 μA when powered by a 1.5 V single supply. The LDO regulator boasts a dropout voltage of 300 mV, enabling it to deliver up to 100 mA of load current. Simulation results show that the undershoot voltage is only 63.7 mV when the load current jumps from 0 to 100 mA with edge of 100 ns, while employing a 100 pF capacitance load. The recovery time to return to equilibrium post this abrupt change is approximately 0.15 μs. The proposed OCL-LDO regulator exhibits a substantial enhancement in transient response compared to its predecessors, alongside a harmonized balance between line regulation and load regulation performance parameters.

A novel gain boost and slew rate enhanced CMOTA

Abstract The design of a novel current mirror operational transconductance amplifier is proposed to address the issues of low gain and limited swing rate under conditions of low voltage and power consumption. In order to improve the gain and swing rate of the amplifier, the increase and lift technology and swing rate increase technology are introduced to the traditional op-amp Simulation and verification based on 0.18 μm BCD process and candence. The results show that under 10 pF load capacitance, the gain is increased by 42 dB and the swing rate is increased by 130 times compared with the conventional transconductance op amp.

A Low-Power Capacitorless LDO Regulator with Transient Enhancement Structure

In this paper, a portable low-power low dropout regulator (LDO) with no output capacitance has been designed in 0.18-[Formula: see text]m CMOS technology. In this paper, a PMOS power transistor is used and combined with an overshoot and undershoot suppression circuit to improve the transient response of the circuit. A modified Class-AB operational transconductance amplifier (OTA) is used to reduce power consumption and act as an error amplifier to eliminate low frequency poles. At the same time, a super source follower and a Miller capacitor are used for frequency compensation of the system. Finally, the system can provide a stable voltage for a load step from 0.2 to 25[Formula: see text]mA in 500[Formula: see text]ns edge-time for 140[Formula: see text]pF-load capacitance. The test results show that the circuit achieves a good voltage regulation rate and high transient response.

Dynamically controllable current reference technique for current-feedback low dropout regulator

This paper proposes the dynamically controllable current reference (DCCR) technique for a wide input range, transient enhancement current-feedback low dropout regulator (WTELDO) to achieve transient enhancement. Combined with a transient enhanced current mirror (TE-CM) adopting an enhanced active resistance network, this technique which is designed based on dynamic bias improves the slewing rate of the power transistor gate but also increases the loop bandwidth. Finally, this WTELDO can reduce the minimum input voltage due to the current-feedback technique and improve the transient response under the condition of maintaining low quiescent current. This designed WTELDO was fabricated in SMIC 0.18μm CMOS process. The input voltage range is 0.8–2.2 V. The output voltage is 0.64 V. The maximum load current is 50 mA and the static current consumption is about 26 μA. Its maximum current efficiency is up to 99.948%. The test results show that the overshoot is 117.5 mV and the undershoot is 167.5 mV when the load current is switched between 0 mA and 50 mA within 300 ns under a 100 pF load capacitor.

Three-Stage Operational Amplifier with Frequency Compensation Using Cascade Zero

Short channel MOSFET exhibits the characteristics of wide bandwidth and low DC gain. A low DC gain causes a high gain error and a narrow output linear range in the closed loop. The DC gains can be improved by using the cascade structure, but frequency compensation is required due to the increase in the number of poles. The output nodes of each stage in a cascade Common-Source amplifier have a cascade of zero, and this zero is cancelled out by the input node of the next stage. This paper proposes a three-stage operational amplifier (op-amp) with frequency compensation using cascade zero. This op-amp was implemented in the 180 nm CMOS technology and achieved 86.96 MHz unity–gain frequency, 51.7° phase margin at 32 pF load capacitor and 99.83 dB DC gain, that is, a 36.21 dB improvement over a two-stage op-amp with the same power consumption. The op-amp consumed 7.74 mW with a supply voltage of 1.8 V.

A High Performance 0.3 V Standard-Cell-Based OTA Suitable for Automatic Layout Flow

In this paper, we propose a novel standard-cell-based OTA architecture based on an improved version of the differential to single-ended converter, previously proposed by the authors, on a novel standard-cell-based basic voltage amplifier block. Due to a replica-bias approach, the basic voltage amplifier exhibits a well-defined output static voltage to allow easy cascadability. Another feature of the basic voltage amplifier is to provide a low output impedance to allow dominant pole compensation at the output of the cascade of several stages. An ultra-low voltage (ULV) standard-cell-based OTA based on the proposed architecture and building blocks has been designed referring to the standard-cell library of a 130-nm CMOS process with a supply voltage of 0.3 V. The layout of the OTA has been implemented by following an automatic layout flow within a commercial tool for the place-and-route of digital circuits. Simulation results have shown a differential gain of 50 dB with a gain–bandwidth product of 10 MHz when driving a 150 pF load capacitance. Good robustness is achieved under PVT variations, in particular for voltage gain, offset voltage, and phase margin. State-of-the-art small signal figures of merit and limited area footprint are key characteristics of the proposed amplifier.

A fast transient response current-feedback low-dropout regulator with dynamic current-enhancement technique

This paper proposed a dynamic current-enhancement technique based on AC coupling network and feedforward compensation capacitor for current-feedback low-dropout regulators (LDOs). Compared with traditional reported current-feedback LDOs, this design exhibits wider input voltage range, greater load capacity and fast transient response, yet no extra power consumption is introduced. Moreover, a complete stability analysis under full load range is given in this paper. The proposed LDO is fabricated in SMIC 0.18μm CMOS process. The input voltage range is 0.8–2.2 V and the maximum load current is 50 mA. The experiment results indicate that the overshoot and undershoot are 76 mV and 141 mV respectively when the load current is varied from 0 to 50 mA within 300 ns under the load of 100 pF load capacitor.

A Standard-Cell-Based CMFB for Fully Synthesizable OTAs

In this paper, we propose a fully standard-cell-based common-mode feedback (CMFB) loop with an explicit voltage reference to improve the CMRR of pseudo-differential standard-cell-based amplifiers and to stabilize the dc output voltage. This latter feature allows robust biasing of operational transconductance amplifiers (OTAs) based on a cascade of such stages. A detailed analysis of the CMFB is reported to both provide insight into circuit behavior and to derive useful design guidelines. The proposed CMFB is then exploited to build a fully standard-cell OTA suitable for automatic place and route. Simulation results referring to the standard-cell library of a commercial 130 nm CMOS process illustrated a differential gain of 28.3 dB with a gain-bandwidth product of 15.4 MHz when driving a 1.5 pF load capacitance. The OTA exhibits good robustness under PVT and mismatch variations and achieves state-of-the-art FOMs also thanks to the limited area footprint.

A push-pull FVF based LDO voltage regulator with slew rate enhancement at the gate of power transistor

A low-dropout (LDO) voltage regulator based on a push-pull flipped voltage follower cell with slew rate improvement at the gate of power transistor is presented. The proposed three-stage regulator exploits two separate signal paths by cross-coupled common-gate cells to improve the transient response and loop stability with low power consumption. Moreover, a slew rate enhancement technique is employed at the gate of power transistor by adding a new current signal path which also improves the small-signal behavior. It is simulated in Cadence with a 90 nm CMOS process, 2.1 μW minimum power dissipation, and 150 mV dropout voltage for 0.9–1.2 V input voltage. It is stable over a range of 40 μA–100 mA load currents and 100 pF load capacitor. The achieved settling time is about 1.2 μs when the load current changes from 40 μA to 100 mA with 200 ns rise time. The obtained line and load regulations are 0.4 mV/V and 6 μV/mA, respectively.

A 4 GHz Single-to-Differential Cross-Coupled Variable-Gain Transimpedance Amplifier for Optical Communication

This letter presents an inductorless transimpedance amplifier (TIA) for visible light communication, using the UMC 40 nm CMOS process. It consists of a single-to-differential input stage with a modified cross-coupled regulated cascode design, followed by a modified fT-doubler mid-stage with a combined active inductor and capacitive degeneration design for bandwidth-enhancement and differential output. The mid-stage also has an attached common-mode feedback (CMFB) circuit. Both the input and mid-stages have gain-varying and peaking-varying functions. It has a measured gain range of 37.5–58.7 dBΩ and 4.15 GHz bandwidth using a 0.5 pF capacitive load. The gain range results in an input dynamic range of 33.2 µA–1.46 mA. Its input referred noise current is 10.7 pA/Hz, core DC power consumption is 7.84 mW from a VDDTIA of 1.6 V and core area is 39 µm × 26 µm.

A High-Speed Fully Differential Telescopic Op-Amp for Active Filter Designs in V2X Applications

In this paper, an ultra-wideband fully differential two-stage telescopic 65-nm CMOS op-amp is presented, which uses low-voltage design techniques such as level shifter circuits and low-voltage cascode current mirrors. The designed op-amp consists of two stages. While the telescopic first stage provides high speed and low swing, the second stage provides high gain and large swing. Common-mode feedback circuits (CMFB), which contain five transistors OTA and sensing resistors, are used to set the first-stage output to a known value. The designed two-stage telescopic operational amplifier has 41.04[Formula: see text]dB lower frequency gain, 1.81[Formula: see text]GHz gain-bandwidth product (GBW) and 51.9∘ phase margin under 5[Formula: see text]pF load capacitance. The design consumes a total current of 11.9[Formula: see text]mA from a 1.2-V supply voltage. Presented fully differential two-stage telescopic op-amp by using low-voltage design techniques is suitable for active filter in vehicle-to-everything (V2X) applications with 120[Formula: see text][Formula: see text]m[Formula: see text]m layout area.

A Novel OTA Architecture Exploiting Current Gain Stages to Boost Bandwidth and Slew-Rate

A novel architecture and design approach which make it possible to boost the bandwidth and slew-rate performance of operational transconductance amplifiers (OTAs) are proposed and employed to design a low-power OTA with top-of-class small-signal and large-signal figures of merit (FOMs). The proposed approach makes it possible to enhance the gain, bandwidth and slew-rate for a given power consumption and capacitive load, achieving more than an order of magnitude better performance than a comparable conventional folded cascode amplifier. Current mirrors with gain and a push–pull topology are exploited to achieve symmetrical sinking and sourcing output currents, and hence class-AB behavior. The resulting OTA was implemented using the 130 nm STMicroelectronics process, with a supply voltage of 1 V and a power consumption of only 1 µW. Simulations with a 200 pF load capacitance showed a gain of 92 dB, a unity-gain frequency of 141 kHz, and a peak slew-rate of 30 V/ms, with a phase margin of 80°, and good noise, PSRR and CMRR performance. The small-signal and large-signal current and power FOMs are the highest reported in the literature for comparable amplifiers. Extensive parametric and Monte Carlo simulations show that the OTA is robust against process, supply voltage and temperature (PVT) variations, as well as against mismatches.

A cryogenic low power CMOS analog buffer at 4.2K

A novel power-efficient analog buffer at liquid helium temperature is proposed. The proposed circuit is based on an input stage consisting of two complementary differential pairs to achieve rail-to-rail level tracking. Results of simulation based on SMIC 0.18um CMOS technology show the high driving capability and low quiescent power consumption at cryogenic temperature. Operating at single 1.4 V supply, the circuit could achieve a slew-rate of +51 V/us and -93 V/us for 10 pF capacitive load. The static power of the circuit is only 79uW.

Design of high gain and high bandwidth operational transconductance amplifier (OTA)

ABSTRACT A novel operational transconductance amplifier (OTA) having high gain and high bandwidth for high-speed analog communication techniques and precision filtering is designed in this paper. The designed OTA uses β-multiplier-based current biasing scheme with folded cascode amplifier scheme in order to improve the small signal models and the DC gain of circuit. The OTA design was carried out using TSMC 65 nm CMOS technology using Cadence Virtuoso tool with 1 V supply voltage and 10 pf capacitive load. The output DC gain was found to be approximately 75.3 dB. In addition, the unity gain frequency for the designed OTA was found to be around 200 MHz. Superior common mode rejection ratio, power supply rejection ratio and slew rates along with compact chip area and low power are other salient features of the designed OTA. The designed OTA can be employed in order to design high performance analog circuits like data converters, phase-locked loops, etc.

A low noise CMOS instrumentation amplifier for TMR-effect-based magnetic sensors

This paper presents a low [Formula: see text] noise CMOS single-ended output instrumentation amplifier (IA) for tunneling magnetic resistance (TMR) sensors. For high DC gain and linearity, the amplifier employs three-stage current-feedback topology. For high CMRR and PSRR, the first two stages employ fully differential input. To maintain stability and lower the power dissipation, the amplifier employs trans-conductance with capacitance feedback compensation (TCFC) topology. The amplifier employs chopping technology and continuous-time AC-coupled ripple reduction loop to reduce [Formula: see text] noise and chopping ripple. The whole chip is fabricated using 0.35 [Formula: see text]m CMOS-BCD technology and the total area is 1 mm2. Test result shows an input-referred noise power spectral density (PSD) of 14 nV/[Formula: see text] is achieved with 1 Hz [Formula: see text] corner. The bandwidth is larger than 50 kHz [Formula: see text] with 20 pF load capacitor. The total current is 300 [Formula: see text]A at 5 V supply.

Ultra-Wide Bandwidth Fully Differential CMOS Opamp with a Novel Bandwidth Extension Technique for SoC Active Filter Applications

An ultra-wide bandwidth fully differential two-stage 65[Formula: see text]nm CMOS operational amplifier (Opamp) is presented, which uses a novel bandwidth extension technique called “pole duplication”. This technique is based on relocating the dominant pole with the same location with a non-dominant pole and adjusting 3-dB frequency and stability with a compensation network. Simulation results show that the proposed Opamp has 103[Formula: see text]MHz 3-dB bandwidth with a 2[Formula: see text]pF load capacitor. It consumes 9[Formula: see text]mA current from 1.2-V supply. Transition frequency of 2.4[Formula: see text]GHz and a gain of 29[Formula: see text]dB is accomplished. A 2[Formula: see text]pF load capacitance can be driven at a phase margin of [Formula: see text]. The suggested pole duplication technique is used to achieve higher 3-dB cut-off frequencies by adjusting the load capacitor. Fully differential two-stage Opamp is presented, which uses a novel bandwidth extension technique, is suitable for SoC active filter applications with 40[Formula: see text][Formula: see text]m layout area and ultra-wide 3-dB bandwidth.

Self-Biased and Supply-Voltage Scalable Inverter-Based Operational Transconductance Amplifier with Improved Composite Transistors

This paper deals with a single-stage single-ended inverter-based Operational Transconductance Amplifiers (OTA) with improved composite transistors for ultra-low-voltage supplies, while maintaining a small-area, high power-efficiency and low output signal distortion. The improved composite transistor is a combination of the conventional composite transistor and forward-body-biasing to further increase voltage gain. The impact of the proposed technique on performance is demonstrated through post-layout simulations referring to the TSMC 180 nm technology process. The proposed OTA achieves 54 dB differential voltage gain, 210 Hz gain–bandwidth product for a 10 pF capacitive load, with a power consumption of 273 pW with a 0.3 V power supply, and occupies an area of 1026 μm2. For a 0.6 V voltage supply, the proposed OTA improves its voltage gain to 73 dB, and achieves a 15 kHz gain–bandwidth product with a power consumption of 41 nW.

Improved Frequency Compensation Technique for Three-Stage Amplifiers

Improved frequency compensation is proposed for a three-stage amplifier with reduced total capacitance, improved slew rate, and reduced settling time. The proposed compensation uses an auxiliary feedback to increase the total effective compensation capacitance without loading the output node. The proposed compensation scheme is validated in simulation by implementing a three-stage amplifier driving 10 pF load capacitor in a 0.18 μm CMOS process. A detailed comparison of the compensation with a conventional nested Miller compensation is also presented. The simulation results showed a reduction in total compensation capacitance and improvement in slew rate compared to conventional nested Miller compensation and the other reported techniques in the literature.

A 0.3 V, Rail-to-Rail, Ultralow-Power, Non-Tailed, Body-Driven, Sub-Threshold Amplifier

A novel, inverter-based, fully differential, body-driven, rail-to-rail, input stage topology is proposed in this paper. The input stage exploits a replica bias control loop to set the common mode current and a common mode feed-forward strategy to set its output common mode voltage. This novel cell is used to build an ultralow voltage (ULV), ultralow-power (ULP), two-stage, unbuffered operational amplifier. A dual path compensation strategy is exploited to improve the frequency response of the circuit. The amplifier has been designed in a commercial 130 nm CMOS technology from STMicroelectronics and is able to operate with a nominal supply voltage of 0.3 V and a power consumption as low as 11.4 nW, while showing about 65 dB gain, a gain bandwidth product around 3.6 kHz with a 50 pF load capacitance and a common mode rejection ratio (CMRR) in excess of 60 dB. Transistor-level simulations show that the proposed circuit outperforms most of the state of the art amplifiers in terms of the main figures of merit. The results of extensive parametric and Monte Carlo simulations have demonstrated the robustness of the proposed circuit to PVT and mismatch variations.