pF Capacitive Load Research Articles

Ultra low voltage, high performance operational transconductance amplifier and its application in a tunable Gm-C filter

This paper presents an ultra low voltage, high performance Operational Transconductance Amplifier (OTA) and its application to implement a tunable Gm-C filter. The proposed OTA uses a 0.5V single supply and consumes 60μw. Employing special CMFF and CMFB circuits has improved CMRR to 138dB in DC. Using bulk driven input stage results in higher linearity such that by applying a 500mvp–p sine wave input signal at 2MHz frequency in unity gain closed loop configuration, third harmonic distortion for output voltage is −46dB and becomes −42.4dB in open loop state for 820mvp–p output voltage at 2MHz. DC gain of the OTA is 47dB and its unity gain bandwidth is 17.8MHz with 20pF capacitance load due to both deliberately optimized design and special frequency compensation technique. The OTA has been used to realize a wide tunable Gm-C low-pass filter whose cutoff frequency is tunable from 1.4 to 6MHz. Proposed OTA and filter have been simulated in 0.18μm TSMC CMOS technology with Hspice. Monte Carlo and temperature dependent simulation results are included to forecast the mismatch and temperature effects after fabrication process.

Impedance Adapting Compensation for Low-Power Multistage Amplifiers

A power-efficient frequency compensation topology, Impedance Adapting Compensation (IAC), is presented in this paper. This IAC topology has, on one hand, a normal Miller capacitor, which is still needed to provide an internal negative feedback loop, and on the other hand, a serial RC impedance as a load to the intermediate stage, improving performance parameters such as stability, gain-bandwidth product and power dissipation. A three-stage IAC amplifier was implemented and fabricated in a 0.35 μm CMOS technology. Experiment results show that the implemented IAC amplifier, driving a 150 pF load capacitance, achieved a gain-bandwidth product (GBW) of 4.4 MHz while dissipating only 30 μW power with a 1.5 V supply.

An Ultra Low-Voltage and Low-Power OTA Using Bulk-Input Technique and Its Application in Active-RC Filters

This paper presents the design of a two-stage bulk-input pseudo-differential operational transconductance amplifier (OTA) and its application in active-RC filters. The OTA was designed in 90 nm CMOS process and operates at a single supply voltage of 0.5 V. Using a two-path bulk-driven OTA by the combination of two different amplifiers the DC gain and speed of the OTA is increased. Rail-to-rail input is made possible using the transistor’s bulk terminal as in input. Also a Miller-Feed-forward (MFF) compensation is utilized which is improved the gain bandwidth (GBW) and phase margin of the OTA. In addition, a new merged cross-coupled self-cascode pair is used that can provide higher gain. Also, a novel cost-effective bulk-input common-mode feedback (CMFB) circuit has been designed. Simplicity and ability of using this new merged CMFB circuit is superior compared with state-of-the-art CMFBs. The OTA has a 70.2 dB DC gain, a 2.5 MHz GBW and a 70.8o phase margin for a 20 PF capacitive load whereas consumes only 25 µw. Finally, an 8th order Butterworth active Biquadrate RC filter has been designed and this OTA was checked by a typical switched-capacitor (SC) integrator with a 1 MHz clock-frequency.

A COMPACT HIGH-SPEED LOW-POWER RAIL-TO-RAIL BUFFER AMPLIFIER FOR STEP-PULSE SIGNALS

A compact high-speed low-power rail-to-rail buffer amplifier, which is suitable for driving heavy capacitive loads, is proposed. The buffer amplifier is composed of a pair of push-pull output transistors with two feedback loops consisting of a pair of complementary error amplifiers and a pair of complementary common-source amplifiers. The buffer draws little current while static but has a large driving capability while transient. A mutual bias scheme is also proposed to reduce the power consumption and the die area for LCD applications. An experimental prototype buffer amplifier implemented in a 0.35 μm CMOS technology demonstrates that the settling time is 1.5 μs for a voltage swing of 0.1 ~ (VDD–0.1) V under a 600 pF capacitance load. Quiescent current of 4 μA is measured. The area of this buffer is 32 × 109 μm2.

A constant-gm and high-slew-rate operational amplifier for an LCD driver

To drive the backplane of a liquid crystal display device and achieve different kinds of grey levels, a high-slew-rate operational amplifier with constant-gm input stage is presented. A Zener-diode structure is inserted between the tails of the complementary input pairs to keep the gm of the input stage constant. A novel slew rate enhancement circuit is implemented to achieve a very high slew rate. The chip has been implemented in a 0.5 μm CMOS process and the chip area of the operational amplifier circuit is 0.11 mm2. The testing results indicate that in the 5–8 V input range, the maximum gm fluctuation is only 4.2%. The result exhibits a high slew rate of 111 V/μs and 102 V/μs for the rising and falling edges under a 20 pF capacitance load, and the low frequency gain is up to 109 dB with a phase margin of 70 °C.

Design procedure for two-stage CMOS opamp with optimum balancing of speed, power and noise

This article presents a basic two-stage CMOS opamp design procedure that provides the circuit designer with a means to establish optimised balancing between speed, power and noise for a given load condition. The proposed design steps allow opamp designers to optimise the power consumption for the given constraints of settling time, accuracy, noise and load. The key factor is to establish the optimum combination of ratios of transconductance of second stage to first stage and load capacitor to compensation capacitor. So, required accuracy and settling time can be established with minimum power consumption. Unlike the earlier reported design procedures, in this article a systematic method is presented to set the quiescent voltages at the transistors of the first and second stages of the opamp. This work will be helpful to select appropriate method of implementation of Miller compensation for given constraints. To verify the viability of the proposed design steps, SPICE simulation results for the proposed procedure are given. Best simulation results obtained on Tanner tool show settling time and power dissipation equal to 320 ns and 188.5 μW, respectively, for 5 pf capacitive load.

A Rail-To-Rail Class-AB Amplifier With an Offset Cancellation for LCD Drivers

A rail-to-rail amplifier with an offset cancellation, which is suitable for high color depth and high-resolution liquid crystal display (LCD) drivers, is proposed. The amplifier incorporates dual complementary differential pairs, which are classified as main and auxiliary transconductance amplifiers, to obtain a full input voltage swing and an offset canceling capability. Both offset voltage and injection-induced error, due to the device mismatch and charge injection, respectively, are greatly reduced. The offset cancellation and charge conservation, which is used to reduce the dynamic power consumption, are operated during the same time slot so that the driving period does not need to increase. An experimental prototype amplifier is implemented with 0.35-mum CMOS technology. The circuit draws 7.5 muA static current and exhibits the settling time of 3 mus, for a voltage swing of 5 V under a 3.4 kOmega resistance, and a 140 pF capacitance load with a power supply of 5 V. The offset voltage of the amplifier with offset cancellation is 0.48 mV.

A monolithic based NIRS front-end wireless sensor

This paper concerns a novel analog front-end of a wireless brain oxymeter smart sensoring instrument based on near-infrared spectroreflectometry (NIRS). The NIRS sensor makes use of dynamic threshold transistors (DTMOS) for low voltage (1V), low power and low noise enhancement. The design is composed of a transimpedance amplifier (TIA) and an operational transconductance amplifier (OTA). The OTA differential input pairs use DTMOS devices for input common mode range enhancement. The OTA was fabricated in a standard 0.18μm CMOS process technology. Measurements under a 5pF capacitive load for the OTA gave a DC open loop gain of 67dB, unity frequency gain bandwidth of 400kHz, input and output swings of 0.58 and 0.7V, a power consumption of 18μW, and an input referred noise of 134nV/√Hz at 1kHz without any extra noise reduction techniques. The achieved features of the proposed oxymeter front-end will allow ultra low-light level measurements, high resolution and good temperature stability.

56.3: A High‐Speed Low‐Power Rail‐to‐Rail Buffer Amplifier for LCD Driver Application

AbstractA high‐speed low‐power rail‐to‐rail buffer amplifier, which is suitable for liquid crystal display driver application, is proposed. The buffer draws little current while static but has a large driving capability while transient. The circuit achieves the low dc power consumption but large driving capability by employing the variable‐gain amplifiers to sense the transients of the input to turn on the output transistors, which are statically off in the stable state. This increases the speed of the circuit without increasing static power consumption too much. An experimental prototype output buffer implemented in a 0.35‐μm CMOS technology demonstrates that the circuit can operate under a wide power supply range. Quiescent current of 5 μA is measured. The buffer exhibits the settling times of 1.5 μs for a voltage swing of 0.1 ∼ (VDD – 0.1) V under a 600 pF capacitance load. The area of this buffer is 30×98μm2.

High-Speed Logic Circuitry Using Bootstrapped and Low-Temperature Polysilicon (LTPS) Technologies for TFT-LCD Panels

In this paper, a high-speed logic circuitry using bootstrapped and low-temperature polysilicon (LTPS) technologies for TFT-LCD panels is proposed. The new circuitry realizes high-speed operation owing to the application of a logic-swing voltage that is wider than the power-supply voltage using bootstrapped technology. As a result, the new logic circuitry can be operated at an operational frequency around 3-10 times higher than that of the conventional circuitry under the conditions of a 0.5 pF load capacitor at the output of a noninverting buffer and +10 V power-supply voltages. The new circuit is named BST-TFT logic circuitry.

P-222L: Late-News Poster: A Compact High-Speed Low-Power Rail-to-Rail Class-B Buffer Amplifier for LCD Application

A compact high-speed low-power rail-to-rail class-B buffer amplifier, which is suitable for liquid crystal display applications, is proposed. The amplifiers are biased by each other to reduce the power consumption and the die area. The buffer draws little current while static but has a large driving capability while transient. The circuit achieves the large driving capability by employing simple comparators to sense the transients of the input to turn on the output stages, which are statically off in the stable state. This increases the speed of the circuit without increasing static power consumption too much. An experimental prototype output buffer implemented in a 0.35-μm CMOS technology demonstrates that the circuit can operate under a wide power supply range. Quiescent current of 4 μA is measured. The buffer exhibits the settling time of 1.5 μs for a voltage swing of 0.1 ∼ (VDD − 0.1) V under a 600 pF capacitance load. The area of this buffer is 32 × 109 μm2.

A novel feed-forward compensation technique for single-stage fully-differential CMOS folded cascode rail-to-rail amplifier

This paper presents a novel active and passive mixed feed-forward compensation technique for single-stage CMOS folded-cascode rail-to-rail operational trans-conductance amplifiers (OTA). Simulations using 0.5 μm Agilent CMOS process parameters indicate a phase margin of around 82° with an unity gain bandwidth of 320 MHz (@1.17 pF capacitive load including the device parasitics). Also, the compensated OTA provided over 60 dB DC-gain with rail-to-rail output voltage swing as well as wide input common-mode range. This ensures optimum step response (fast and accurate settling without ringing) for the feedback amplifier in switched-capacitor signal processing applications. An improved ``fast sensing'' common-mode feedback circuit with high common-mode gain is also used for the single-stage cascode OTA.

Low-voltage power-efficient adaptive biasing for CMOS amplifiers and buffers

Novel adaptive biasing techniques, suited for low-voltage operation, are presented. They provide small and accurately controlled quiescent currents, which are automatically boosted when an input signal is applied. Measurement results of an OTA using these techniques and fabricated in a 0.5 µm CMOS technology show a slew rate of more than 40 V/µs for an 80 pF load capacitance and a static power consumption of only 140 µW.

A New Dynamic Latch Offset Measurement Technique For Offset Cancellation

This paper introduces a new technique that uses a differential amplifier in closed-loop negative feedback configuration to measure the offset of a dynamic latch. This offset can then be stored and canceled using standard techniques, thus allowing gain reduction in the preamplifier stages in high-resolution comparators. Input offset storage was used to cancel the offset of the feedback differential amplifier itself without adding any extra timing overhead. A complementary metal oxide semiconductor (CMOS) comparator was designed based on the proposed technique. The comparator consists of a preamplifier followed by a dynamic latch with series capacitors in between to cancel the offsets of both stages. The output of the comparator drives a 1 pF load capacitance and is held valid for at least 75% of the cycle. The performance of the comparator was simulated using HSPICE with the worst-case combination of differences as large as 10 mV between the thresholds of nominally identical transistors, where it achieved an offset of 400 μV at a 40 MHz clock rate in 0.6 μ CMOS technology while dissipating 1 mW from a 3.3 V power supply.

A 0.8 /spl mu/m CMOS pixel IC for low energy X-ray spectroscopy with on-chip detector

A charge sensitive readout chain has been developed for pixel applications with small die area and low power dissipation. The overall measured gain is 500 mV/fC; the ENC is 15.3e rms@15 fF; the power dissipation is 1.5 mW@3.3 V with 30 pF load capacitance; the active die area is 270 /spl mu/m/spl times/270 /spl mu/m. A detector has been integrated on the same substrate with the electronics. It consists of a 20 /spl mu/m/spl times/20 /spl mu/m diode, which is DC coupled to the input of the readout chain. The IC has been designed and fabricated in a 0.8 /spl mu/m commercially available CMOS technology. A series of tests has been performed employing X-ray sources with energies from 2.3 to 3.3 keV. The experimental results are reported and the noise characteristics of the system are evaluated. With a FWHM of less than 300 eV in room temperature, low energy X-ray spectroscopy is clearly feasible using an integrated detector element in commercial CMOS technology.

Low-power CMOS OTA input stages and voltage buffers based on adaptive biasing topology

In this article, a new CMOS low-voltage (1.8V) low-power (80μW) operational transconductance amplifier input stage is described. This is based on class-AB adaptive biasing topology presented in the work by Cardarilli (G. Cardarilli, G. Ferri, M. Re, Microelectronics Journal 30(3) (1999) 223–228), which allows us to decrease quiescent power consumption without degradation of transient characteristics. In fact its slew rate is about 45V/μs, for a 1pF capacitive load. The main adaptive biasing topology is also used to realize a low-voltage (1.5V) low-power (0.89μW) high slew rate (168V/μs) rail-to-rail voltage buffer. Spice simulations, demonstrating the validity of the proposed technique, are presented.

A BiCMOS wideband operational amplifier with 900 MHz gain-bandwidth and 90 dB DC gain

A fully differential operational amplifier has been designed and fabricated for analog-to-digital converter application. The amplifier mainly consists of folded cascode structure with current source as output loads and common-mode feedback circuits. The technique of feed-forward compensation is used in order to improve the settling time and gain bandwidth (GBW) of this amplifier. This amplifier is integrated in 0.8 /spl mu/m BiCMOS process with an active die area of 0.1 mm/sup 2/. The DC gain of this amplifier is 90 dB. The GBW and phase margin of this amplifier is 900 MHz and 47/spl deg/, respectively. The power dissipation is minimized by using BiCMOS technology and is about 25 mW for 2 pF load capacitance.

Characterization and improvement of GaAs HEMT analog switches for sampled-data applications

This paper presents design consideration and experimental comparison of GaAs HEMT analog switches for high-speed and high-precision sampled-data applications. At first, basic pass-transistor switches fabricated in a 0.5-/spl mu/m GaAs HEMT technology are measured for characterization of transient errors induced due to clock-feedthrough and charge transfer. In order to improve the switch dynamic performances, a dual dummy transistor compensation technique is used and related driver circuitry is developed. On-wafer measurements demonstrate that the improved switch provides a significant reduction of the transient errors, a reasonable dynamic range, and a high isolation. The switch with a 0.53 pF load capacitor achieves a total harmonic distortion below -55 dB and -38 dB at 10 MHz and 1.0 GHz clock frequency, respectively. >

An adjustable output driver with a self-recovering Vpp generator for a 4M×16 DRAM

An adjustable output driver with a self-recovering Vpp generator for a 4 M/spl times/16 DRAM (dynamic random-access memory) is presented. Its driver characteristics can easily be changed between fast mode and slow mode in the assembly process. The driver with a small inductance load operates 2.5 ns faster in fast mode than in slow mode, and the driver in slow mode reduces the initial drive current and prevents ringing waveforms even with large inductance load. With a 5 pF capacitance load and 20 cm wire, the ringing amplitude in slow mode is reduced to 1/3 that of the fast mode. Users can choose the operation mode of the output driver according to their application. The self-recovering Vpp generators feed 16 output drivers and control the generator capacity according to the data pattern to supply the same amount of Vpp charge consumed by output drivers. The Vpp generator saves 3.9 mA on average at a 25 ns read cycle.

Bipolar-Complementary-Metal-Oxide-Semiconductor (BiCMOS) Technology with Polysilicon Self-Aligned Bipolar Devices

An advanced bipolar-complementary-metal-oxide-semiconductor (BiCMOS) technology providing uncompromised high-performance, double polysilicon self-aligned (PSA) n-p-n bipolar and 1.25 µm gate length CMOS transistors is described. The polysilicon self-aligned-BiCMOS technology (PSA-BiCMOS) is intended for high-speed logic circuit operation at 5 V, where a high level of circuit integration and power consumption is involved. Features include vertical n-p-n transistors with a self-aligned n+ polysilicon emitter and p+ polysilicon base. The CMOS transistor features n+ polysilicon gates and lightly doped drain (LDD) NMOSFET. A process simulator, Stanford University process engineering models (SUPREM III) and device simulator, Poisson and continuity equation solver (PISCES II) were used to optimize the process steps and to enhance device characteristics, respectively. The performance of N- and PMOS transistors is comparable to those of a conventional CMOS process. The driving capability of CMOS and PSA-BiCMOS was compared according to fan-out. Compared to CMOS, PSA-BiCMOS has good driving capability from about 2.5 fan-out and PSA-BiCMOS with 1.25 µm N- and PMOS transistors and a bipolar transistor with 2 µm emitter width exhibits an average ring oscillator delay of 6.25 ns/stage at 1 pF load capacitance at 5 V.