Bipolar-Complementary-Metal-Oxide-Semiconductor (BiCMOS) Technology with Polysilicon Self-Aligned Bipolar Devices

Abstract

An advanced bipolar-complementary-metal-oxide-semiconductor (BiCMOS) technology providing uncompromised high-performance, double polysilicon self-aligned (PSA) n-p-n bipolar and 1.25 µm gate length CMOS transistors is described. The polysilicon self-aligned-BiCMOS technology (PSA-BiCMOS) is intended for high-speed logic circuit operation at 5 V, where a high level of circuit integration and power consumption is involved. Features include vertical n-p-n transistors with a self-aligned n+ polysilicon emitter and p+ polysilicon base. The CMOS transistor features n+ polysilicon gates and lightly doped drain (LDD) NMOSFET. A process simulator, Stanford University process engineering models (SUPREM III) and device simulator, Poisson and continuity equation solver (PISCES II) were used to optimize the process steps and to enhance device characteristics, respectively. The performance of N- and PMOS transistors is comparable to those of a conventional CMOS process. The driving capability of CMOS and PSA-BiCMOS was compared according to fan-out. Compared to CMOS, PSA-BiCMOS has good driving capability from about 2.5 fan-out and PSA-BiCMOS with 1.25 µm N- and PMOS transistors and a bipolar transistor with 2 µm emitter width exhibits an average ring oscillator delay of 6.25 ns/stage at 1 pF load capacitance at 5 V.