Low-power CMOS OTA input stages and voltage buffers based on adaptive biasing topology

Abstract

In this article, a new CMOS low-voltage (1.8 V) low-power (80 μW) operational transconductance amplifier input stage is described. This is based on class-AB adaptive biasing topology presented in the work by Cardarilli (G. Cardarilli, G. Ferri, M. Re, Microelectronics Journal 30(3) (1999) 223–228), which allows us to decrease quiescent power consumption without degradation of transient characteristics. In fact its slew rate is about 45 V/μs, for a 1 pF capacitive load. The main adaptive biasing topology is also used to realize a low-voltage (1.5 V) low-power (0.89 μW) high slew rate (168 V/μs) rail-to-rail voltage buffer. Spice simulations, demonstrating the validity of the proposed technique, are presented.