Abstract
Designing a low-power high slew rate operational amplifier (OPA) is focused in this paper. There are three stages in this design. First, N and P complementary differential pairs (DP) were used to amplify input signals with low input offset. The second stage was a push-pull common source amplifier to boost the total voltage gain higher. In this stage, Miller feedback was employed to make the amplifier stable. The output stage adopted the super buffer technique to make this stage operated in a class AB mode. The amplitude of the output voltage was also pushed to the power supply rails at this output stage. In the design of the first and the last stages, we employed the flipped voltage follower (FVF) as the building block to pursue low quiescent bias current, large dynamic range and high slew rate at the same time. The output resistance at the output stage was reduced by local feedback. This circuit was designed based on TSMC 0.35μm CMOS technology. At present, the simulation exhibit good performance parameters, In the simulation results, we obtained a voltage gain over 130 dB with a unit-gain bandwidth larger than 80 MHz where its input offset voltage is smaller than 10 pV. The estimated slew rate was higher than 30 V/μs. This fact would promise our circuit to be a high performance operational amplifier for general applications.
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