Abstract
A novel, inverter-based, fully differential, body-driven, rail-to-rail, input stage topology is proposed in this paper. The input stage exploits a replica bias control loop to set the common mode current and a common mode feed-forward strategy to set its output common mode voltage. This novel cell is used to build an ultralow voltage (ULV), ultralow-power (ULP), two-stage, unbuffered operational amplifier. A dual path compensation strategy is exploited to improve the frequency response of the circuit. The amplifier has been designed in a commercial 130 nm CMOS technology from STMicroelectronics and is able to operate with a nominal supply voltage of 0.3 V and a power consumption as low as 11.4 nW, while showing about 65 dB gain, a gain bandwidth product around 3.6 kHz with a 50 pF load capacitance and a common mode rejection ratio (CMRR) in excess of 60 dB. Transistor-level simulations show that the proposed circuit outperforms most of the state of the art amplifiers in terms of the main figures of merit. The results of extensive parametric and Monte Carlo simulations have demonstrated the robustness of the proposed circuit to PVT and mismatch variations.
Highlights
The scaling of CMOS technology, and the diffusion of applications requiring very low power consumption, such as IoT (Internet of Things) nodes [1,2] or biomedical and wearable devices [3,4], have paved the way to the development of compact and ultralow voltage (ULV) circuits
This bias voltage is applied to the gates of the NMOS transistors of the input stage, setting its bias current to a scaled replica of the reference current
The gate control voltage VA is exploited to set the output common voltage of the first stage using a common mode feed-forward (CMFF) technique: In the left part of Figure 2, the reference current is mirrored through devices Mb4 -Mb5 and applied to Mb6 -Mb7 that are a replica of the P-part of the input stage and are diode connected
Summary
The scaling of CMOS technology, and the diffusion of applications requiring very low power consumption, such as IoT (Internet of Things) nodes [1,2] or biomedical and wearable devices [3,4], have paved the way to the development of compact and ultralow voltage (ULV) circuits. In BD amplifiers [8,9,10,11,12,13], the body is used as input terminal instead of the gate, allowing the input dc level not to be constrained by the threshold voltage of the devices, at the cost of reduced transconductance gain, higher noise, and an input impedance that is not purely capacitive In this context, Ferreira et al proposed a Miller amplifier designed in 350 nm CMOS process and operating at a supply voltage of 0.6 V in 2007 [8]. Inverter-based solutions [15,16,17,18] exploit the CMOS inverter, or inverter-like structures, such as the Arbel cell [19], as building blocks that allow rail-to-rail signal swing with reduced supply voltages In these structures, the elimination of the bias current generator of the differential pair worsens the common mode rejection (CMRR) and results in large variations of small signal parameters under PVT variations.
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