A push-pull FVF based LDO voltage regulator with slew rate enhancement at the gate of power transistor

Abstract

A low-dropout (LDO) voltage regulator based on a push-pull flipped voltage follower cell with slew rate improvement at the gate of power transistor is presented. The proposed three-stage regulator exploits two separate signal paths by cross-coupled common-gate cells to improve the transient response and loop stability with low power consumption. Moreover, a slew rate enhancement technique is employed at the gate of power transistor by adding a new current signal path which also improves the small-signal behavior. It is simulated in Cadence with a 90 nm CMOS process, 2.1 μW minimum power dissipation, and 150 mV dropout voltage for 0.9–1.2 V input voltage. It is stable over a range of 40 μA–100 mA load currents and 100 pF load capacitor. The achieved settling time is about 1.2 μs when the load current changes from 40 μA to 100 mA with 200 ns rise time. The obtained line and load regulations are 0.4 mV/V and 6 μV/mA, respectively.