Performance Of Thin-film Transistors Research Articles

Performance evaluation of polycrystalline Si1−xGex thin-film transistors fabricated by continuous-wave laser lateral crystallization on glass substrates

This study was aimed at elucidating the performance of continuous-wave laser lateral-crystallized (CLC) polycrystalline Si1−xGex (poly-Si1−xGex) thin-film transistors (TFTs). The transfer characteristics of the n-ch CLC poly-Si1−xGex TFTs (x = 0, 0.05, 0.1, and 0.3) exhibited a positive shift in the threshold voltage (Vth) with increasing Ge content. Furthermore, the off-current in the p-ch CLC poly-Si0.9Ge0.1 TFTs decreased with decreasing film thickness. These properties of the CLC poly-Si1−xGex TFTs can be attributed to the generation of acceptors and increment of gate SiO2/poly-Si1−xGex interface charge state with increasing Ge content. The generation of acceptors was also supported by Hall effect measurements. In addition, the thermal stability of acceptors up to 700 °C was elucidated through Hall effect measurements and TFT performance evaluations. Furthermore, we examined the origins of these acceptors. This experiment highlighted the sensitivity of Si1−xGex to Ge incorporation, even in small amounts.

Effect of Oxygen Plasma Treatment on the Performance of GQDs-Modulated InGaZnO Thin-Film Transistors

Effect of Oxygen Plasma Treatment on the Performance of GQDs-Modulated InGaZnO Thin-Film Transistors

Channel thickness effect on the performance of amorphous SiZnSnO semiconductor thin-film transistor with metal capping structure

Channel thickness effect on the performance of amorphous SiZnSnO semiconductor thin-film transistor with metal capping structure

Correlation between CO2 Sensitivity and Channel-Layer Thickness in In2O3 Thin-Film Transistor Gas Sensors

CO2 monitoring is important for achieving net-zero emissions. Here, we report on a CO2 gas sensor based on an In2O3 thin-film transistor (TFT), which is expected to realize both low-temperature operation and high sensitivity. The effect of channel thickness on TFT performance is well known; however, its effect on CO2 sensitivity has not been fully investigated. We fabricated In2O3 TFTs of various thicknesses to evaluate the effect of channel thickness on CO2 sensitivity. Consequently, TFT gas sensors with thinner channels exhibited higher CO2 sensitivity. This is because the surface effect is more prominent for a thinner film, suggesting that charge transfer between gas molecules and the channel surface through gas adsorption has a significant impact on changes in the TFT parameters in the subthreshold region. The results showed that the In2O3 TFT in thin channels is a promising candidate for CO2-sensitive TFT gas sensors and is useful for understanding an effect of gas adsorption in oxide TFTs with a very thin channel as well.

High-performance of low temperature solution-processed P-channel CuGaO thin film transistors

The exploration of p-type metal-oxide semiconductors (MOS) has garnered growing interest, particularly for their potential applications in next-generation optoelectronic devices, display backplanes, and low-power consumption complementary MOS (CMOS) circuits. Here, we introduced low-temperature solution-processed copper gallium oxide (CuGaO) films for p-channel thin-film transistors (TFTs). Hall Effect measurements confirmed the p-type conduction of CuGaO, revealing a conductivity and mobility of 3.76 ×10−2 S/cm and 7.89 cm2V–1s–1, respectively. The p-channel CuGaO-250 TFT demonstrated a field-effect mobility (μFE) of 1.24 cm2V–1s–1, the lowest subthreshold swing (SS) of 519 mV/dec, and an ON/OFF current ratio (ION/IOFF) of ∼104 at a low operating voltage. The notable improvement in TFT performance can be attributed to the quality of the CuGaO-250 film, a smooth surface morphology, and a reduction of interfacial traps between the semiconductor and the gate insulator. Hence, low-temperature fabrication of the p-channel CuGaO TFT holds promise for implementing metal oxide-based TFT and complementary metal oxide semiconductor (CMOS) circuits in next-generation displays.

High-throughput characterization is key to report reliable organic thin-film transistor performance

High-throughput characterization is key to report reliable organic thin-film transistor performance

Low-temperature preparation and characteristics of top-gate thin-film transistors with La-ZTO active layers and polymethylmethacrylate dielectric layers

A top-gate coplanar-structure thin-film transistor (TFT) combining the advantages of both a co-sputtered amorphous La-doped ZnSnO (a-La-ZTO) active layer and solution-based polymethylmethacrylate (PMMA) gate dielectric layer has been prepared under low temperature (100 °C) with low cost for the first time. The results indicate that the PMMA thin film demonstrates anti-reflection properties when it combines with a-La-ZTO layer to form a double-layer film, displaying high transparency to visible light of ∼90.3%. Moreover, it was found that the La target power during the deposition of a-La-ZTO film plays an important role in suppressing the formation of oxygen vacancies and adjusting the carrier concentration of a-La-ZTO active layer, thus impacting a-La-ZTO TFT performance. Overall, the optimum a-La-ZTO TFT with a La target power of 13.9 W, working in an n-channel enhancement mode, possesses a large saturated mobility (>10 cm2 (Vs)−1) and an on/off drain current ratio over 105.

Evaluation of extremely thin polycrystalline germanium films and their TFT performance fabricated at 400 °C by Cu-induced crystallization on a glass substrate

Germanium (Ge) has high mobility and is more suitable for low-temperature device processes than silicon (Si); thus, it has attracted attention as an upper-layer transistor for monolithic three-dimensional (M3D) integration. We evaluated in detail the crystalline quality of extremely thin polycrystalline-Ge (poly-Ge) thin films thinner than 15 nm fabricated by metal-induced crystallization using copper (Cu-MIC) at 400 °C using micro-Raman scattering, in-plane X-ray diffraction, transmission electron microscopy (TEM), TEM energy dispersive X-ray spectroscopy, and TEM electron diffraction. Additionally, the films were applied to p-ch double-gate (DG) poly-Ge thin-film transistors (TFTs), and their performance was evaluated. As a result, a high I on/I off ratio of 2.8 × 103 was realized by crystallization at 400 °C with a ratio equal to that of crystallization at 500 °C. This study demonstrated the feasibility of Cu-MIC DG poly-Ge TFTs for M3D applications.

Cross-Linked Interfacial Layer for Enhanced Performance in n-Channel Organic Thin Film Transistors

Cross-Linked Interfacial Layer for Enhanced Performance in n-Channel Organic Thin Film Transistors

The Enhanced Performance of Oxide Thin-Film Transistors Fabricated by a Two-Step Deposition Pressure Process.

It is usually difficult to realize high mobility together with a low threshold voltage and good stability for amorphous oxide thin-film transistors (TFTs). In addition, a low fabrication temperature is preferred in terms of enhancing compatibility with the back end of line of the device. In this study, α-IGZO TFTs were prepared by high-power impulse magnetron sputtering (HiPIMS) at room temperature. The channel was prepared under a two-step deposition pressure process to modulate its electrical properties. X-ray photoelectron spectra revealed that the front-channel has a lower Ga content and a higher oxygen vacancy concentration than the back-channel. This process has the advantage of balancing high mobility and a low threshold voltage of the TFT when compared with a conventional homogeneous channel. It also has a simpler fabrication process than that of a dual active layer comprising heterogeneous materials. The HiPIMS process has the advantage of being a low temperature process for oxide TFTs.

Copper(I) Iodide Thin Films: Deposition Methods and Hole-Transporting Performance.

The pursuit of p-type semiconductors has garnered considerable attention in academia and industry. Among the potential candidates, copper iodide (CuI) stands out as a highly promising p-type material due to its conductivity, cost-effectiveness, and low environmental impact. CuI can be employed to create thin films with >80% transparency within the visible range (400-750 nm) and utilizing various low-temperature, scalable deposition techniques. This review summarizes the deposition techniques for CuI as a hole-transport material and their performance in perovskite solar cells, thin-film transistors, and light-emitting diodes using diverse processing methods. The preparation methods of making thin films are divided into two categories: wet and neat methods. The advancements in CuI as a hole-transporting material and interface engineering techniques hold promising implications for the continued development of such devices.

Poling induced changes in polarization domain structure of polymer ferroelectrics for application in organic thin film transistors

While electrical poling of organic ferroelectrics has been shown to improve device properties, there are challenges in visualizing accompanying structural changes. We observe poling induced changes in ferroelectric domains by applying differential phase contrast (DPC) imaging in the scanning transmission electron microscope, a method that has been used to observe spatial distributions of electromagnetic fields at the atomic scale. In this work, we obtain DPC images from unpoled and electrically poled polyvinylidene fluoride trifluorethylene films and compare their performance in polymer thin film transistors. The vertically poled films show uniform domains throughout the bulk compared to the unpoled film with a significantly higher magnitude of the overall polarization. Thin film transistors comprising a donor–acceptor copolymer as the active semiconductor layer show improved performance with the vertically poled ferroelectric dielectric film compared with the unpoled ferroelectric dielectric film. A poling field of 80–100 MV/m for the dielectric layer yields the best performing transistors; higher than 100 MV/m is seen to degrade the transistor performance. The results are consistent with a reduction in deleterious charge carrier scattering from ferroelectric domain boundaries or interfacial dipoles arising from electrical poling.

A ternary gate-connected threshold switching thin-film transistor

Multi-valued logic has been a significant focus of research in various fields with the advancement of information technology. One approach to realizing ternary logic is integrating of a threshold switching (TS) device with a transistor, but this method often entails a complex fabrication process. This work suggests a ternary gate-connected threshold switching thin-film transistor (TS-TFT) by serially connecting the TS device with a bottom-gate thin-film transistor (TFT). The fabrication process is simplified with a structure that shares electrodes and insulators. Different threshold voltages from TS and TFT devices produce stable multiple states. The Pt/HfO2/TiN TS device has an electronic trapping/detrapping switching mechanism that exhibits low power consumption and high reliability. With the superior electrical performance of an amorphous indium gallium zinc oxide TFT, the TS-TFT has stable endurance. Furthermore, pulse switching and ternary inverter are demonstrated from the practical point of view.

High mobility and hysteresis free InGaSnO thin film transistors by co-sputtering via low temperature post annealing process

In this work, InGaSnO thin film transistors (TFTs) with high mobility (>50 cm2/Vs) were prepared by a simple co-sputtering process at a low temperature of 150 ℃. In the co-sputtering process of InSnO and Ga2O3, the composition of InGaSnO can be reasonably controlled by adjusting the sputtering power in the radio frequency plasma, which significantly affects the electrical performance and stability of InGaSnO TFTs. The highly overlapping 5 s electron cloud of In and Sn and the high binding energy of Sn-O lay the foundation for the high mobility of InGaSnO TFTs. The defects related to oxygen in the channel are suppressed by the reasonable control of the composition of Ga in the multicomponent oxides. Meanwhile, the interface defects between the gate dielectric and the active layer are reduced, and a dense metal-oxygen-metal network is formed which is conducive to electron transmission. We have achieved an InGaSnO TFTs with mobility of 58.7 cm2/Vs and threshold voltage of -1.33 V. The stability under positive and negative bias stress is also significantly improved. In general, a simple co-sputtering process is entirely feasible to realize high-mobility oxide TFTs. The control of the process temperature below 150 ℃ also extends its application in flexible electronic devices.

Enhanced performance in doped micro-nano porous organic thin-film transistors

Molecular doping, as an effective technique for controlling the electrical property of organic semiconductors (OSCs) by introducing additional charges, has been proven to adjust important device parameters in organic thin-film transistors (OTFTs). Doping highly crystalline OSCs without disrupting structural order is a crucial challenge, as it significantly affects the charge carrier mobility. Here, we demonstrate a molecular doping method without disrupting the molecular ordering to improve the charge carrier mobility of 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C8-BTBT) based OTFTs via a simple thermal spin-coating method. The key is to introduce micro-nano pores into C8-BTBT thin-film for channel doping, which is achieved by mixing with the unsubstituted BTBT as it can be easily removed from the thin-film through an ordinary annealing process. Micro-nano pores allow the dopant molecules (2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane, F4-TCNQ) to access the conductive channel of OTFT, which is beneficial for charge injection. Indeed, we further discover that F4-TCNQ doped porous C8-BTBT thin-films exhibit better charge mobility than those of neat and F4-TCNQ doped C8-BTBT films in OTFTs. This work proposes an effective way to expose OSC conjugated core to the dopant, which not only improves the charge transfer reaction between organic/dopant semiconductor through cofacial stacking, but also reduces the trap density and contact resistance.

Cation doping strategy for improved carrier mobility and stability in metal-oxide Heterojunction thin-film transistors

The heterojunction channel architecture has emerged as a viable solution to enhance the performance of metal-oxide thin-film transistors (TFTs), addressing the performance limitations of single-channel counterparts. However, carrier mobility enhancement through a channel thickness design often encounters significant challenges such as the negative threshold voltage (Vth) shift. In this study, we present a cation doping strategy, designed to regulate Vth shift while simultaneously boosting carrier mobility in zinc-tin-oxide (ZTO)-based heterojunction TFTs. A comprehensive investigation of ZTO-based semiconductors was conducted to explore the impact of cation doping on the energy band structure and to find an optimal heterojunction channel structure for high carrier mobility and stability. The resulting ZTO/Ti-doped ZTO (Ti:ZTO) heterojunction TFTs demonstrated a field-effect mobility of 39.7 cm2/Vs, surpassing the performance of ZTO TFTs (16.1 cm2/Vs), with a minimal change in the Vth. Furthermore, the ZTO/Ti:ZTO TFTs exhibited enhanced bias-stress stability compared to the ZTO TFTs. We attribute the improved mobility and stability to the electron accumulation near the oxide channel heterointerface facilitated by band bending and defect passivation effect arising from the Ti:ZTO back-channel layer, respectively.

C-Axis Aligned Composite InZnO via Thermal Atomic Layer Deposition for 3D Nanostructured Semiconductor.

Amorphous oxide semiconductors have been widely studied for various applications, including thin-film transistors (TFTs) for display backplanes and semiconductor memories. However, the inherent instability, limited mobility, and complexity of multicomponent oxide semiconductors for achieving high aspect ratios and conformality of cation distribution remain challenging. Indium-zinc oxide (IZO), known for its high mobility, also faces obstacles in instability resulting from high carrier doping density and low ionization energy. To address these issues and attain a balance between mobility and stability, adopting a highly aligned structure such as a c-axis aligned crystalline IGZO could be advantageous. However, limited studies have reported enhanced electrical performance using crystalline IZO, likely attributed to the high thermal stability of the individual components (In2O3 and ZnO). Here, we first propose a c-axis aligned composite (CAAC) IZO with superior TFT properties, including a remarkable performance of field-effect mobility (μFE) of 55.8 cm2/(V s) and positive-bias-temperature-stress stability of +0.16 V (2 MV/cm, 60 °C, 1 h), as well as a low subthreshold swing of 0.18 V/decade and hysteresis as 0.01 V, which could be obtained through optimization of growth temperature and composition using thermal atomic layer deposition. These results surpass those of TFTs based on nanocrystalline/polycrystalline/amorphous-IZO. We conducted a thorough investigation of CAAC-IZO and revealed that the growth temperature and cation distribution profoundly influence the crystal structure and device properties. Finally, we observed excellent compositional conformality and 97% step coverage of IZO on a high-aspect-ratio (HAR) structure with an aspect ratio reaching 40:1, which is highly promising for future applications. Our results include a detailed investigation of the influence of the crystal structure of IZO on the film and TFT performance and suggest an approach for future applications.

Amine‐ and Polyethylene glycol‐Functionalized Pyrediyne Quantum Dots for Bioimaging Applications

AbstractPyrediyne, a recent addition to the 2D organic nanomaterials family, is known for its improved electrical conductivity, which can have potential applications in the performance of thin film transistors, field effect transistors, and charge storage devices. It has been shown that similar to carbon quantum dots, pyrediyne quantum dots (PDYQDs) can also be generated from 2D pyrediyne nanosheets and can be utilized for imaging cancer cells. In this context, it is highly desirable to enhance the photoluminescence properties of PDYQDs in order to improve the quality of quantum dots‐based cell imaging techniques. Herein, PDYQDs are effectively functionalized using aqueous functionalization agents such as NH3, PEG200, and PEG20000 via a simple and cost‐effective methodology, which resulted in a significant enhancement in the emission quantum yield (QY) (up to 30.2 %) through effectively reducing the non‐radiative recombination centers. After confirming their cytocompatibility using in vitro studies, the amine‐functionalized PDYQDs were utilized for imaging L929 mouse fibroblast cells. The findings in the present study suggest that it is worth exploring various surface functionalization techniques to enhance the applications of novel carbon‐based nano‐structures in various biological and optoelectronic devices.

Effect of temperature modulation on the performance of top contact bottom gate organic thin film transistor

This research article investigates the influence of temperature variations on the performance parameters of Top Contact Bottom Gate (TCBG) Organic Thin Film Transistors (OTFTs). Employing the Arrhenius equation and Schottky emission model, the study explores temperature-dependent charge carrier mobility and injection mechanisms. Analyzing a wide range of parameters, the research unveils a complex interplay between temperature and OTFT behavior. The linear and saturation mobilities exhibit a decline due to enhanced carrier-phonon interactions and lattice vibrations. Transconductance and ION/IOFF ratio display a concomitant decrease at higher temperatures, indicative of the heightened susceptibility of OTFT performance to temperature fluctuations. The depreciation in subthreshold slope and threshold voltage with rising temperatures underscores the influence of temperature on trap states. The research emphasizes the importance of considering temperature’s impact during OTFT design for diverse applications, enhancing the reliability and functionality of organic electronic devices.

Effect of source and drain electrode positions on the performance of bottom gate organic thin film transistor

In recent years several novel technologies have emerged on commercial level. Organic electronics is one such technology that has created new avenues for the development of flexible, robust, and cost-effective electronic devices. Transistor developed using organic materials are called organic thin film transistors (OTFT). Transistor is elementary component of any electronic device, any variation in the size or performance of the transistors reflects directly on the overall performance of the electronic devices. Bottom gate bottom contact (BGBC) OTFT is commonly employed single gate organic transistor owing to its simple architecture and easy fabrications. Since in organic semiconductor material carrier mobility of charges is lower, hence its overall performance declines. As a result, its application in electronic circuits becomes limited. Therefore, to enhance the performance of BGBC OTFT and facilitate the optimal charge mobilisation inside organic semiconductor layer i.e., OSC, improvement in the architecture of BGBC is deemed necessary. In this research article the performance of BGBC OTFT is analysed for different positions of electrodes viz. source and drain embedded inside the OSC layer. The study signifies the effect of electrode positions on performance optimization of BGBC OTFT without changing the materials, dimensions, or the operating voltage regime. It has been found that for 30 nm thick OSC layer, the electrodes should ideally be placed between 5 nm to 10 nm above the junction of OSC and dielectric layer inside OSC layer for optimal results.