Pass Transistor Logic Research Articles

A 5.4 <formula formulatype="inline"><tex Notation="TeX">$\mu{\rm W}$</tex></formula> Soft-Decision BCH Decoder for Wireless Body Area Networks

This paper presents an IEEE 802.15.6 compliant soft-decision BCH decoder for energy-constrained wireless body area networks. The proposed soft-decision decoder (SDD) provides a 1 dB coding gain compared to the hard-decision decoder (HDD). The improvement in BER performance can translate into power savings at the transmitter. The energy dissipation and area of the soft-decision BCH decoder is minimized by jointly considering the algorithm, architecture, and circuit parameters. An early termination strategy is proposed to reduce the number of redundant test patterns. Probabilistic sorting is proposed to determine the test patterns, and its hardware complexity is only 54.7% of the conventional sorting method. The HDD kernel is implemented by adopting the Peterson rule, reducing the area by 44.2%. A pass-transistor logic based Chien search circuit consumes 33.3% less energy compared to the standard-cell based implementation. The chip is designed to operate at the minimum energy point of 0.29 V, yielding an energy reduction of 94% compared to a direct-mapped SDD at SNR=5 dB. Fabricated in 90 nm CMOS, the chip dissipates 5.4 μW at 500 kHz, achieving a throughput of 6.38 Mbps.

Comparative Analysis of Full Adders Using different MOS Technologies

With the development in the fabrication techniques the numbers of the transistors on a chip are increasing at much faster rate, results in the very large scale integration. This paper discusses the comparative analysis of full adder circuits in terms of higher speed and size. All these three parameters depend upon each other and trade-off exists within these. A 4bit adder is designed using different MOS technologies These Techniques include CMOS technology designing with transmission gate and designing adder with combination of Complimentary Pass Logic and Transmission gate & simulated using 180nm, 130nm & 100nm technology files Keywords-CM OS Transmission Gate (TG), Pass-Transistor Logic (PTL), Co mp lementary Pass transistor Logic (CPL),), fu ll adder Power, Delay, Channel Length. I. INTRODUCTION The extensive development in the field integrated circuits has intensified the research efforts in low power microelectronics. The low-power, high speed, small size design has become a major design consideration. This largely affects the design complexity of many Function units such as multip lier and algorithmic logic unit (A LU). The limited power supply capability of present battery technology has made power consumption an important issue in portable devices. The speed of the design is limited by size of the transistors, parasitic capacitance and delay in the critical path. The driving capability of a full adder is very important as full adders are mostly used in cascade configuration, where the output of one provides the input for other. If the fu ll adders lack driving capability then it requires additional buffer, wh ich consequently increases the power dissipation. In the last decade, the full adder has gone through substantial improvement in power consumption, speed and size, but at the cost of weak driving capability and reduced voltage swing. However, reduced voltage swing has the advantage of lower power consumption (1). There is no ideal full adder cell that can be used in all types of applications (2). Hence novel architectures such as CMOS Transmission Gate (TG), Pass-Transistor Logic (PTL), Co mp lementary and Pass-transistor Logic (CPL) (3) their co mb inations (Hybrid) are co mmonly used in designing full adder cells are proposed to meet the requirements. Each design style has its own share of advantages and disadvantages. In this paper, a brief description of the evolution of full adder circuits in terms of lesser power consumption, higher speed and lesser chip size given. Initially the most conventional 28 transistor full adder is imp lemented and then gradually full adders consisting of as less as 14 t ransistors are discussed which are simulated using different technology files 10n m, 130n m and 100n m.

Organic integrated circuits for information storage based on ambipolar polymers and charge injection engineering

Ambipolar semiconducting polymers, characterized by both high electron (μe) and hole (μh) mobility, offer the advantage of realizing complex complementary electronic circuits with a single semiconducting layer, deposited by simple coating techniques. However, to achieve complementarity, one of the two conduction paths in transistors has to be suppressed, resulting in unipolar devices. Here, we adopt charge injection engineering through a specific interlayer in order to tune injection into frontier energy orbitals of a high mobility donor-acceptor co-polymer. Starting from field-effect transistors with Au contacts, showing a p-type unbalanced behaviour with μh = 0.29 cm2/V s and μe = 0.001 cm2/V s, through the insertion of a caesium salt interlayer with optimized thickness, we obtain an n-type unbalanced transistor with μe = 0.12 cm2/V s and μh = 8 × 10−4 cm2/V s. We applied this result to the development of the basic pass-transistor logic building blocks such as inverters, with high gain and good noise margin, and transmission-gates. In addition, we developed and characterized information storage circuits like D-Latches and D-Flip-Flops consisting of 16 transistors, demonstrating both their static and dynamic performances and thus the suitability of this technology for more complex circuits such as display addressing logic.

Monte-Carlo analysis of a new 6-T full-adder cell for power and propagation delay optimizations in 180 nm process

Purpose – Demand and popularity of portable electronic devices are driving the designers to strive for higher speeds, long battery life and more reliable designs. Recently, an overwhelming interest has been seen in the problems of designing digital systems with low power at no performance penalty. Most of the very large-scale integration applications, such as digital signal processing, image processing, video processing and microprocessors, extensively use arithmetic operations. Binary addition is considered as the most crucial part of the arithmetic unit because all other arithmetic operations usually involve addition. Building low-power and high-performance adder cells are of great interest these days, and any modifications made to the full adder would affect the system as a whole. The full adder design has attracted many designer's attention in recent years, and its power reduction is one of the important apprehensions of the designers. This paper presents a 1-bit full adder by using as few as six transistors (6-Ts) per bit in its design. The paper aims to discuss these issues. Design/methodology/approach – The outcome of the proposed adder architectural design is based on micro-architectural specification. This is a textual description, and adder's schematic can accurately predict the performance, power, propagation delay and area of the design. It is designed with a combination of multiplexing control input (MCIT) and Boolean identities. The proposed design features lower operating voltage, higher computing speed and lower energy consumption due to the efficient operation of 6-T adder cell. The design adopts MCIT technique effectively to alleviate the threshold voltage loss problem commonly encountered in pass transistor logic design. Findings – The proposed adder circuit simulated results are used to verify the correctness and timing of each component. According to the design concepts, the simulated results are compared to the existing adders from the literature, and the significant improvements in the proposed adder are observed. Some of the drawbacks of the existing adder circuits from the literature are as follows: The Shannon theorem-based adder gives voltage swing restoration in sum circuit. Due to this problem, the Shannon circuit consumes high power and operates at low speed. The MUX-14T adder circuit is designed by using multiplexer concept which has a complex node in its design paradigm. The node drivability of input consumes high power to transmit the voltage level. The MCIT-7T adder circuit is designed by using MCIT technique, which consumes more power and leads to high power consumption in the circuit. The MUX-12T adder circuit is designed by MCIT technique. The carry circuit has buffering restoration unit, and its complement leads to high power dissipation and propagation delay. Originality/value – The new 6-T full adder circuit overcomes the drawbacks of the adders from the literature and successfully reduces area, power dissipation and propagation delay.

An Efficient Low Power Ripple Carry Adder for Ultra Applications

The main goal of this paper is to provide new low power solutions for very large scale integration. Designers especially focus on the reduction of the power dissipation which shows increasing growth with the scaling down of the technologies. In this paper various technologies at the different levels of the design process have been implemented to reduce the power dissipation at the circuit, architecture and system levels. Previous technologies are summarized and compared with our new approach is presented in this paper. : The main objective of this project is the reduction of power dissipation by eliminating the PMOS tree and also by utilizing energy stored at the output can be retrieved by the reversing the current source direction discharging process instead of dissipation in NMOS network with DOMINO LOGIC, PASS TRANSISTOR LOGIC. It also increases the performance of circuits. Here for this project, I am using MICROWIND TOOL. By using this tool we can develop schematic for all above techniques and also find out the power dissipation.

Layout Designing for Different Full Adder Topologies at 0.18μm Technology Node

In this paper VLSI layout designing and optimization techniques for different full adder topologies like Complementary MOSFET full adder (CMOS),Transmission gate full adder(TGA),Complementary Pass transistor Logic full adder(CPL) and Domino Full Adder has been discussed. Power consumption and propagation delay are the major issue for low voltage level circuit application designing in recent years. Full adders are the very important circuit element for calculating the basic four mathematical operations (addition, subtraction, multiplication and division) functions in Integrated circuits. In VLSI systems such as microprocessors and application specific DSP architecture are using different full adders for calculating mathematical operations. In this paper one bit full adders topologies has been used for analysis. The layout designing of the basic logic gates and different full adders is done using L-Edit v14.11 Tanner EDA tool using 0.18μm technology node. The results shows that parameters like Power consumption and total propagation delay, for a particular aspect ratio the Transmission Gate Full adder consume less power and having less propagation delay.

Reduction of Leakage Power using Stacking Power Gating Technique in Different CMOS Design Style at 45Nanometer Regime

As transistor sizes scale down and levels of integration increase, leakage power has become a vital downside in modern low-power VLSI technology. This is often very true for ultra-lowvoltage (ULV) circuits, wherever high levels of leakage force designers to selected relatively high threshold voltages, which limits performance. In this paper, we design different design approach of master slave D flip-flop with stacking power gating leakage reduction technique. Here these techniques essentially increase the effective resistance of leakage paths by adding sleep transistors between logic stacks and power supply rails. Power gating technique also provides many of the property from transistor stacking technique. The proposed approach saves maximum amount of the Leakage power without degrading the performance of the circuit. In this work we analyses the leakage power of three different types of CMOS design style such as pass transistor logic (PTL), transmission gates and gate diffusion input (GDI) design. All these proposed circuits are simulated with and without the application of leakage reduction techniques. The circuits are simulated using Cadence Virtuoso tool at 45nm technology for various parameters.

HYBRID-CMOS LOGIC STYLE DESIGN FOR FAST SELF-CHECKING ADDERS DATA PATHS

In this paper we present an efficient design for self-checking fast adders data paths. We investigate the implementation of concurrent error detection fast adders: carry look-ahead, Carry skip, Carry-select and Conditional-Sum adders. To achieve a low overhead, low power design, we use hybrid-CMOS logic style and combine Conventional CMOS and CMOS Pass transistor Logic (CPL). The proposed schemes are Totally Self-Checking (TSC). They are fully differential and checked by dual-rail and parity codes.

Low Power Pulsed Flip-Flop using Self Driven Pass Transistor Logic

paper, a low power implicit type pulsed flip-flop (PFF) using self-driven pass transistor logic is presented. The pulse generation logic comprising of two transistor AND gate is used in the critical path of the design for improved speed and reduced complexity. The pass transistor logic driven by generated clock pulse is used directly to drive the output of the flip-flop. The proposed design is compared with the conventional implicit type data close to output (ip-DCO) flip- flop. As compared to the conventional pulse triggered flip- flop, the proposed pulsed flip-flop (PFF) design features best speed, power and power-delay-product performance. The proposed technique is implemented using HSPICE CMOS 90nm technology. The average power consumption for 50% switching activity is reduced by 12.75% as compared to conventional ip-DCO. Keywordsow power, pulsed flip-flop, pass transistor logic, critical

High Performance and Function Design on the Transistor Level

paper proposes a new design of pass transistor logic based 2T AND gate. Performance comparison of proposed gate with traditional CMOS, complementary pass-transistor logic design and GDI techniques is presented. Different methods have been compared with respect to the number of devices, power-delay product, temperature sustainability and noise immunity in order to prove the superiority of proposed design over existing ones. The simulation has been carried out on Tanner EDA tool on BSIM3v3 90nm technology. Keywordsgate, PTL and Power-delay product.

Low Power-Area Designs of 1Bit Full Adder in Cadence Virtuoso Platform

Power consumption has emerged as a primary design constraint for integrated circuits (ICs). In the Nano meter technology regime, leakage power has become a major component of total power. Full adder is the basic functional unit of an ALU. The power consumption of a processor is lowered by lowering the power consumption of an ALU, and the power consumption of an ALU can be lowered by lowering the power consumption of Full adder. So the full adder designs with low power characteristics are becoming more popular these days. This proposed work illustrates the design of the low-power less transistor full adder designs using cadence tool and virtuoso platform, the entire simulations have been done on 180nm single n-well CMOS bulk technology, in virtuoso platform of cadence tool with the supply voltage 1.8V and frequency of 100MHz. These circuits consume less power with maximum (6T design)of 93.1% power saving compare to conventional 28T design and 80.2% power saving compare to SERF design without much delay degradation. The proposed circuit exploits the advantage of GDI technique and pass transistor logic

P.19: Density‐of‐States Based Device‐Circuit Co‐Design Platform for Solution‐Processed Organic Integrated Circuits

AbstractIn this work, we propose the subgap density‐of‐states (DOS) based device‐circuit co‐design platform for solution‐processed organic integrated circuits. For the circuit simulation, analytical I‐V and C‐V model were established from experimentally extracted DOS parameters, incorporated into HSPICE via Verilog‐A, and verified by comparing the simulation result with the measured characteristics of inverter integrated with solution‐processed polymer‐based organic thin‐film‐transistors. Furthermore, as the case study, it was shown by using our well‐calibrated simulation platform that the pass‐transistor type logic was potentially promising in low‐power and high‐speed solution processed organic integrated circuits.

A Novel and High Performance Implementation of 8x8 Multiplier based on Vedic Mathematics using 90nm Hybrid PTL /CMOS Logic

Power consumption plays an imperative role specifically in the field of VLSI today, every designer be it an analog circuit or a digital circuit designer is concerned about the amount of power his or her circuit is going to consume in the end. The core of this paper consist of the introduction of a novel and high performance design of an 8x8 multiplier using ancient Indian mathematics called Vedas. This paper presents four different designs which includes 8x8 Vedic multiplier and 8x8 array multiplier implementation using CMOS and Hybrid PTL/ CMOS logic style and finally proved that Hybrid PTL(Pass Transistor Logic)/CMOS design of Vedic Multiplier is the best among all these implementations .The multiplier and the adder-subtractor units used for the implementation of Vedic multiplier are adopted from ancient methodology of India mathematics called as Vedas. The use of Vedas not only abates the carry propagation taking place from LSB to MSB but also produces the partial product and there sums in the same step. Vedic mathematics based multipliers thus causes least delay and consume least power among these four multipliers. The functionality of all the four designs and there PDP and power calculations at three different frequencies and four different voltages were calculated on 90 nm CMOS technology using tanner EDA 13.0v.The proposed Hybrid PTL/CMOS implementation of Vedic multiplier is up to 34.29% power efficient and about 49.82% speedy as compared to the conventional CMOS implementation of array multiplier.

Low‐power 6‐GHz wave‐pipelined 8 b × 8 b multiplier

In this study, a low-power, high-speed, layout-efficient 8 b × 8 b unsigned parallel multiplier based on pair-wise algorithm with wave-pipelining is introduced. Simplified interconnection and data propagation in forward direction with no feedback in pair-wise multiplication technique is the key to achieve high-performance wave-pipelined multiplier. In the proposed work, normal process complementary pass-transistor logic is used to build all the leaf cells of combinational block. The input/output registers are designed with high-performance pulse-triggered true single-phase clocking flip flop. Post-layout simulation with Taiwan Semiconductor Manufacturing Company Limited 0.18 μm single-poly double-metal complimentary metal oxide semiconductor technology using Tanner EDA V.13 shows that the proposed multiplier works at 6.25 GHz clock frequency and achieves the throughput of 6.25 billion multiplications per second with average power dissipation of 18.54 mW and overall latency of 3.24 ns at 25°C temperature and at 2 V supply rail.

A NEW REDUCED CLOCK POWER FLIP-FLOP FOR FUTURE SOC APPLICATIONS

In this paper a novel technique is proposed based on the comparison between Conventional Conditional Data Mapping Flip-flop and Clock Pair Shared D flip flop(CPSFF) here we are checking the working of CDMFF and the conventional D Flip-flop. Due to the immense growth in nanometer technology the SOC is became the future concept of the modern electronics the number of clock transistors are also considerably increased. In this paper we propose a new system which will considerably reduce the number of transistor which will lead to the reduction in clocking power which will improve the overall power consumption.Our proposed which is designed using Pass Transistor Logic (LCPTFF) Low Power Clocked Pass Transistor Flip-Flop system is showing much better output than all other designs as mentioned in the tabulation.The simulations are done using Microwind& DSCH analysis software tools and the result between all those types are listed below.

Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL

Asynchronous adiabatic logic (AAL) is a novel lowpower design technique which combines the energy saving benefits of asynchronous systems with adiabatic benefits. In this paper, energy efficient full adder using double pass transistor with asynchronous adiabatic logic (DPTAAL) is used to design a low power multiplier. Asynchronous adiabatic circuits are very low power circuits to preserve energy for reuse, which reduces the amount of energy drawn directly from the power supply. In this work, an 8×8 multiplier using DPTAAL is designed and simulated, which exhibits low power and reliable logical operations. To improve the circuit performance at reduced voltage level, double pass transistor logic (DPL) is introduced. The power results of the proposed multiplier design are compared with the conventional CMOS implementation. Simulation results show significant improvement in power for clock rates ranging from 100 MHz to 300 MHz.

Design of Efficient Complementary Pass Transistor based Modified Booth Encoder Array Multiplier

paper a method to build a faster array multiplier based on Radix 4 Modified Booth Encoder - which is broadly used for the signed multiplication applications- with less area and power is presented. This is achieved by optimizing the overall interconnection delay in the partial product array and by scheming the most efficient Full Adder and Booth Encoder in Complementary Pass Transistor Logic approach. The proposed array multiplier's performance in terms of delay, power and area is compared with conventional as well as Baugh-Wooley Multiplier. In order to optimize the power and area of the multiplier, a CPL Based MBE with standard partial product array is proposed and designed in full custom style. The use of efficient 10 Transistor based Full adders based on CPL logic ensures that the entire design is in CPL logic, which provides a regular outline with less interconnection intricacy.

Monte-Carlo Analysis of a New 6-T Full-Adder Cell for Power and Propagation Delay Optimizations in 180nm Process

This paper presents a 1-bit full adder by using as few as six transistors per bit in its design. It is designed with a combination of multiplexing control input and Boolean identities. The proposed design features lower operating voltage, higher computing speed and lower energy consumption due to the efficient operation of 6-transistor adder cell. The design adopts Multiplexing with Control input technique to alleviate the threshold voltage loss problem commonly encountered in pass transistor logic design. The proposed design successfully embeds the buffering circuit in the full adder design and the transistor count is minimized. The improved buffering helps the design operate under lower supply voltage compared with existing works. It also enhances the speed performance of the cascaded operation significantly while maintaining the performance edge in energy consumption. For performance comparison, the proposed full adder is evaluated along with four existing full adders via extensive BSIM4 simulation. The simulation results, 180nm process models, indicate that the proposed design has lowest energy consumption per addition along with the performance edge in both speed and energy consumption makes it suitable for low power and high speed embedded processor applications.

ULPD and CPTL Pull-Up Stages for Differential Cascode Voltage Switch Logic

Two new structures for Differential Cascode Voltage Switch Logic (DCVSL) pull-up stage are proposed. In conventional DCVSL structure, low-to-high propagation delay is larger than high-to-low propagation delay this could be brought down by using DCVSL-R. Promoting resistors in DCVSL-R structure increase the parasitic effects and unavoidable delay and it also occupies more area on the chip (Turker et al., 2011). In order to minimize these problems, a new Ultra-Low-Power Diode (ULPD) structures in place of resistors have been suggested. This provides the minimum parasitic effects and reduces area on the chip. Second proposed circuit uses Complementary Pass Transistor Logic (CPTL) structure, which provides complementary outputs. This contributes an alternate circuit for conventional DCVSL structure. The performances of the proposed circuits are examined using Cadence and the model parameters of a 180 nm CMOS process. The simulation results of these two circuits are compared and presented. These circuits are found to be suitable for VLSI implementation.

Reversed signal propagation BDD based low‐power pass‐transistor logic synthesis

AbstractBinary decision diagrams (BDDs) are the most frequently used data structure for the representation and manipulation of Boolean functions in the area of Very Large Scale Integration (VLSI) CAD. In this paper, we propose the reversed‐signal‐propagation (RSP) BDD‐based low‐power pass‐transistor logic (PTL) synthesis. In RSP BDD, the signal flow direction is opposite to that of the forward BDD. So the power supply is taken as a root node and the terminal nodes 0 and 1 represent the function in its normal and complement form. We propose an efficient way to construct the multi‐output function RSP BDD and its PTL realization. Simulation results of the proposed method give lower power consumption and high performance as a result of reduced switching activity than the existing techniques. The power improvement is about 70–80% compared to the existing techniques. © 2013 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.