Abstract
In this paper we present an efficient design for self-checking fast adders data paths. We investigate the implementation of concurrent error detection fast adders: carry look-ahead, Carry skip, Carry-select and Conditional-Sum adders. To achieve a low overhead, low power design, we use hybrid-CMOS logic style and combine Conventional CMOS and CMOS Pass transistor Logic (CPL). The proposed schemes are Totally Self-Checking (TSC). They are fully differential and checked by dual-rail and parity codes.
Highlights
Addition is one of the most fundamental operations for digital computations
Interest in on-line error detection continues to grow as VLSI circuits increase in complexity
It presents a Self-Checking (SC) fast adder based on a CMOS pass transistor differential XOR [1]
Summary
Addition is one of the most fundamental operations for digital computations. On-line error detection provides an opportunity for self-diagnosis and self-correction within a circuit design. This work deals with design of fast self-checking adders’ data paths. It presents a Self-Checking (SC) fast adder based on a CMOS pass transistor differential XOR [1]. The proposed schema is a design using hybrid-CMOS logic style combining Complementary pass-transistor logic (CPL) and complementary CMOS. It presents a self checking fast adder based on the use of double-rail and parity encoding to achieve the totally self checking goal
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