Improved Carry Select Adder with Reduced Area and Low Power Consumption

Abstract

ABSTRACT Power dissipation is one of the most important design objectives in integrated circuits, after speed. As adders are the most widely used components in such circuits, design of efficient adder is of much concern for researchers. This paper presents performance analysis of different Fast Adders. The comparison is done on the basis of three performance parameters i.e. Area, Speed and Power consumption. We present a modified carry select adder designed in different stages. Results obtained from modified carry select adders are better in area and power consumption . Categories and Subject Descriptors VHDL, Behavioural modeling, General Terms Carry select adder, multiple stage adder Keywords Adder, Carry select Adder, carry skip adder, VHDL Simulation 1. INTRODUCTION compact Addition usually impacts widely the overall performance of digital systems and a crucial arithmetic function. In electronic applications adders are most widely used. Applications where these are used are multipliers, DSP to execute various algorithms like FFT, FIR and IIR. Wherever concept of multiplication comes adders come in to the picture. As we know millions of instructions per second are performed in microprocessors. So, speed of operation is the most important constraint to be considered while designing multipliers. Due to device portability miniaturization of device should be high and power consumption should be low. Devices like Mobile, Laptops etc. require more battery backup. So, a VLSI designer has to optimize these three parameters in a design. These constraints are very difficult to achieve so depending on demand or application some compromise between constraints has to be made. Ripple carry adders exhibits the most compact design but the slowest in speed. Whereas carry lookahead is the fastest one but consumes more area [2]. Carry select adders act as a compromise between the two adders. In 2002, a new concept of hybrid adders is presented to speed up addition process by Wang et al. that gives hybrid carry look-ahead/carry select adders design [7]. In 2008, low power multipliers based on new hybrid full adders is presented in [8]. In 2008, Hasan Krad et al provided the performance analysis for a 32-Bit Multiplier with a Carry look-ahead Adder and a 32-bit Multiplier with a Ripple Adder using VHDL and showed that CLA multiplier is almost double in speed as compared to RCA multiplier [9]. The rest of the paper is organized as follows. In section 2, a brief about ripple carry adder, carry skip and variable carry skip is given. In the same section carry select adder is introduced along with partitioning methodology. Also a new architecture with clock sharing is introduced. Section 3 provides the results obtained. Section 4 concludes the paper