Design and Analysis of a High Speed Carry Select Adder

Abstract

An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design. High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devising a hybrid CSA. In the proposed adder, CSA uses CLAA technology to generate the carry bits for each sum bit, which are then used to select the respective multiplexer (MUX) which adds the carry bit to the sum accordingly. The proposed adder has been synthesized with bulk 40 nm standard CMOS library on Synopsys Design Compiler. Analysis has indicated the superiority of proposed adder over CLAA and CSA. As compared to CSA and CLAA, the proposed Carry Select Ahead Adder (CSAA) provides shorter average path and a simpler hardware. This has led to faster processing speed by increasing the complexity of circuit on the chip. The proposed adder finds its applications in various Arithmetic and Logic Units (ALU) of CPUs for faster arithmetic results. Keywords—Carry Look Ahead Adder (CLAA), Carry Select Adder (CSA), Multiplexer (MUX), Carry Select Ahead Adder (CSAA), Arithmetic and Logic Unit (ALU).