Comparative Analysis of Full Adders Using different MOS Technologies

Abstract

With the development in the fabrication techniques the numbers of the transistors on a chip are increasing at much faster rate, results in the very large scale integration. This paper discusses the comparative analysis of full adder circuits in terms of higher speed and size. All these three parameters depend upon each other and trade-off exists within these. A 4bit adder is designed using different MOS technologies These Techniques include CMOS technology designing with transmission gate and designing adder with combination of Complimentary Pass Logic and Transmission gate & simulated using 180nm, 130nm & 100nm technology files Keywords-CM OS Transmission Gate (TG), Pass-Transistor Logic (PTL), Co mp lementary Pass transistor Logic (CPL),), fu ll adder Power, Delay, Channel Length. I. INTRODUCTION The extensive development in the field integrated circuits has intensified the research efforts in low power microelectronics. The low-power, high speed, small size design has become a major design consideration. This largely affects the design complexity of many Function units such as multip lier and algorithmic logic unit (A LU). The limited power supply capability of present battery technology has made power consumption an important issue in portable devices. The speed of the design is limited by size of the transistors, parasitic capacitance and delay in the critical path. The driving capability of a full adder is very important as full adders are mostly used in cascade configuration, where the output of one provides the input for other. If the fu ll adders lack driving capability then it requires additional buffer, wh ich consequently increases the power dissipation. In the last decade, the full adder has gone through substantial improvement in power consumption, speed and size, but at the cost of weak driving capability and reduced voltage swing. However, reduced voltage swing has the advantage of lower power consumption (1). There is no ideal full adder cell that can be used in all types of applications (2). Hence novel architectures such as CMOS Transmission Gate (TG), Pass-Transistor Logic (PTL), Co mp lementary and Pass-transistor Logic (CPL) (3) their co mb inations (Hybrid) are co mmonly used in designing full adder cells are proposed to meet the requirements. Each design style has its own share of advantages and disadvantages. In this paper, a brief description of the evolution of full adder circuits in terms of lesser power consumption, higher speed and lesser chip size given. Initially the most conventional 28 transistor full adder is imp lemented and then gradually full adders consisting of as less as 14 t ransistors are discussed which are simulated using different technology files 10n m, 130n m and 100n m.