Partially-depleted SOI Research Articles

On the RF Extrinsic Resistance Extraction for Partially-Depleted SOI MOSFETs

We have investigated the radio frequency (RF) extrinsic resistance extraction for partially-depleted (PD) silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistors (MOSFETs). Although the thick buried oxide in SOI devices can block the substrate coupling, the SOI neutral-body coupling effect is significant for RF applications. An equivalent circuit considering this effect has been proposed. Based on this equivalent circuit, a new model capturing the frequency dependence of extrinsic resistances has been derived. After considering the impact of quasi-neutral body, we have developed a physically accurate RF extrinsic resistance extraction methodology for PD SOI MOSFETs

The C Shape Behavior of the Floating Body Effect in Function of Temperature in PD SOI nMOSFETs

The temperature influence on the gate induced floating body effect in partially depleted (PD) Silicon-on-Insulator (SOI) nMOSFETs is investigated, through experimental results and two- dimensional numerical simulations. A C shape behavior of the transconductance second peak as a function of temperature is observed, due to the competition between two effects: the generation-recombination process and the effective electric field mobility degradation.

Low Leakage SOI CMOS Static Memory Cell With Ultra-Low Power Diode

A new CMOS digital storage device is developed based on the combination of two reverse biased composite CMOS diodes, each of them featuring ultra-low leakage and a negative impedance characteristic in reverse mode. The biasing of MOS transistors in very weak inversion, with negative gate-to-source voltages, results in a static current that lays orders of magnitude below that of conventional cross-coupled CMOS inverters. Based on our device, a 7-transistors SRAM cell is presented. Modeling, simulation and experimental characterization of the main properties of this cell are reported for a 0.13 mum partially-depleted SOI CMOS process. The feasibility of ultra-low leakage memory circuits is demonstrated experimentally by the design of a 256 times 1 bits SRAM column.

Effect of Silicon Thickness on Contact-Etch-Stop-Layer-Induced Silicon/Buried-Oxide Interface Stress for Partially Depleted SOI

In this letter, based on both experimental investigations and simulation confirmation, it was found that a strained contact etch stop layer over the thin silicon layer of a partially depleted silicon-on-insulator (PD-SOI) will induce high stress on the buried-oxide/silicon interface. Additionally, the interface stress increases with decrease of silicon thickness TSI, thus enhancing the current of the MOSFET, e.g., as TSI shrinks from 90 to 50 nm, current enhancement for PD-SOI n-channel MOS increased from 7% to 12% due to the increase of interface stress. The results are expected to be more significant for devices with thinner TSI such as fully depleted silicon-on-insulator and multigate devices

Boxes: An Engineering Methodology for Calculating Soft Error Rates in SOI Integrated Circuits

A simple methodology is necessary to characterize the SEU behavior of large quantities of RAM cell types, latches, flip-flops, other logic cells, I/O cells, etc. Such a methodology, called "Boxes", is being used for the Honeywell S150 radiation-hard 0.15 mum partially-depleted SOI process. Using physics-based equations, this paper shows how to break up each critical transistor into several "boxes", each with its own dimensions and critical charge, for the purpose of calculating soft error rate (SER). The Boxes methodology also allows for calculation of SER due to an ion that must simultaneously strike two separated sensitive volumes in order to cause an upset. This can be the dominant upset mechanism for many types of cells such as certain hardened SRAM's and other cells that obtain radiation hardness via extra transistors (such as triple modular redundancy, the DICE latch, etc.). Boxes also predicts upsets that can occur when an ion strike pulls a circuit node below ground or above the positive power supply. The boxes methodology was applied to a 6 T non-hardened SRAM, a hardened SRAM, and a D-type flip-flop. The theoretical predictions correlated well with experimental vertical ion strike data

Study of the linear kink effect in PD SOI nMOSFETs

We present in this work a study of the linear kink effect (LKE) occurrence in partially depleted (PD) SOI nMOSFETs with thin gate oxide. The experimental LKE dependence on the channel length, channel width and drain voltage are reported as well as the impact of various parameters on the second peak has been studied by two-dimensional numerical simulations, namely, the gate current level, the carrier lifetime, the increase of the body potential, the threshold voltage variation and AC analysis. Three-dimensional simulations were also performed in order to evaluate the LKE dependence on the channel width.

Off-state modulation of SOI floating-body

Off-state modulation of the floating-body potential in partially depleted silicon-on-insulator (PDSOI) transistors from the 90-nm technology generation is observed using pulsed current-voltage (I-V) measurements. Varying the off-value of the gate voltage is shown to either decrease the transient on-current (I/sub on,trans/) of PDSOI devices through gate-to-body leakage or increase I/sub on,trans/ due to gate-induced drain leakage. Dependence of I/sub on,trans/ on off-state gate bias is not observed in bulk devices, PDSOI devices with body contacts, or fully depleted SOI devices, confirming the role of floating-body in the observed effects. Thus, off-state conditions should be accounted for when considering floating-body effects and when using pulsed I-V measurements to study self-heating.

Delay testing of partially depleted silicon-on-insulator (PD-SOI) circuits

Partially depleted silicon-on-insulator (PD-SOI) technology has garnered more attention recently with regards to replacing traditional bulk-silicon technology as the mainstream technology of choice for high-performance/low-power digital applications. The increase in performance is due to the buried oxide layer, which provides a dramatic decrease in the source and drain junction capacitance, as well as a reduction in the traditional back biasing resulting from the body effect. The reported performance increases have been between 20% and 35%. However, this increase in performance comes at a cost of complexity from a performance measurement and delay testing perspective. Where the SOI transistor is faster than the bulk transistor, there exists a variation in delay caused by threshold voltage shifts that must be accounted for during manufacturing test. This paper explores these issues and proposes new test techniques for this promising technology

A leakage-tolerant low-swing circuit style in partially depleted silicon-on-insulator CMOS technologies

The parasitic bipolar leakage and the large subthreshold leakage due to high floating-body voltage reduce the noise margin and increase the delay of the circuits in the partially depleted silicon-on-insulator (PD/SOI). Differential cascode voltage switch logic (DCVSL) has circuit topologies susceptible to the leakage currents. In this paper, we propose a new circuit style to effectively handle the leakage problems in PD/SOI DCVSL. The proposed low-swing DCVSL (LS-DCVSL) uses the small internal swing to prevent the body of evaluation transistors from being charged to high voltage and, hence, suppress the leakages in DCVSL. Simulation results show that the proposed LS-DCVSL five-input XOR circuit is 33% faster than DCVSL five-input XOR circuit. In addition, the proposed circuit does not experience noise margin reduction due to pass-gate leakage.

Low-swing current mode logic (LSCML): A new logic style for secure and robust smart cards against power analysis attacks

A new logic style called low-swing current mode logic (LSCML) is presented. It features a dynamic and differential structure and a low-swing current mode operation. The LSCML logic style may be used for hardware implementation of secure smart cards against differential power analysis (DPA) attacks but also for implementation of self-timed circuits thanks to its self-timed operation. Electrical simulations of the Khazad S-box have been carried out in 0.13μm PD (partially depleted) SOI CMOS technology. For comparison purpose, the Khazad S-box was implemented with the LSCML logic and two other dynamic differential logic styles previously reported. Simulation results have shown an improved reduction of the data-dependent power signature when using LSCML circuits. Indeed the LSCML based Khazad S-box has shown a power consumption standard deviation more than two times smaller than the one in DyCML and almost two times smaller than the one in DDCVSL.

Impact of the twin-gate structure on the linear kink effect in PD SOI nMOSFETS

In this work, the influence of the twin-gate structure on the gate-induced floating body effects in thin gate oxide partially depleted (PD) silicon-on-insulator (SOI) nMOSFETs is investigated through two-dimensional numerical simulations, which are validated by experimental results. The asymmetric behavior of the body potential with the interchange of the master and slave transistor of the twin-gate structure will be shown, as well as the relation between the total resistance and the effective mobility degradation factor. It will be demonstrated that a similar reduction of the linear kink effect is obtained in a twin-gate structure and in a conventional SOI transistor with an external resistance in series.

Performance advantages of 3-D digital integrated circuits in a mixed SOI and bulk CMOS design space

Three-dimensional (3-D) integrated circuits (ICs), with multiple stacked device layers, offer a unique design opportunity to use both bulk and partially depleted (PD) silicon-on-insulator (SOI) CMOS devices in a single circuit design. Such 3-D designs can, for example, minimize the body effect common in bulk designs and reduce adverse floating-body effects (FBE) common in PD SOI designs. Sequential 3-D technology such as exfoliation-based single-crystal silicon layer transfer allows a low-temperature approach to 3-D integration with high-density interconnectivity. Using the characteristics of this technology, we present the mixed SOI bulk (MSB) design approach that effectively re-maps conventional VLSI designs to the 3-D design space. Tradeoffs in delay, noise margin, power, and circuit footprint are analyzed and demonstrated through analyzes of static, dynamic, pass-transistor, and SRAM circuits.

Ring Oscillators for CMOS Process Tuning and Variability Control

Test structures utilizing ring oscillators to monitor MOSFET ac characteristics for digital CMOS circuit applications are described. The measurements provide information on the average behavior of sets of a few hundred MOSFETs under high speed switching conditions. The design of the ring oscillators is specifically tailored for process centering and monitoring of variability in circuit performance in the manufacturing line as well as in the product. The delay sensitivity to key MOSFET parameter variations in a variety of ring oscillator designs is studied using a compact model for partially depleted silicon on insulator(PD-SOI) technology, but the analysis is equally valid for conventional bulk Si technology. Examples of hardware data illustrating the use of this methodology are taken primarily from experimental hardware in the 90-nm CMOS technology node in PD-SOI. The design and data analysis techniques described here allow very rapid investigation of the sources of variations in circuit delays.

A Monte Carlo investigation of the RF performance of partially-depleted SOI MOSFETs

A Monte Carlo investigation of the high-frequency performance of partially-depleted silicon-on-insulator MOSFETs is presented. From static current–voltage characteristics to the RF dynamic and noise performance, the simulator is able to properly reproduce the experimental measurements for the device under test with the need of only two model parameters, the rate of diffusive surface scattering mechanisms and the threshold voltage. Once the model is validated for a 90 nm effective gate length device, a forecast of the dynamic and noise performance of the device when the gate length is downscaled is carried out and the influence of scaling on internal transport quantities is discussed.

130-nm Partially Depleted SOI MOSFET Nonlinear Model Including the Kink Effect for Linearity Properties Investigation

In this brief, a nonlinear empirical model is proposed for partially depleted (PD) silicon-on-insulator (SOI) MOSFETs. It is based on an equivalent circuit approach in which the nonlinear elements are described by empirical equations. A new original method is proposed for modeling the kink effect and its frequency dispersion, occurring in floating body PD SOI MOSFETs. The model is validated through large-signal measurements, and the nonlinear properties of PD SOI transistors are studied.

Simulation analysis of the bipolar amplification induced by heavy-ion irradiation in double-gate MOSFETs

The sensitivity to heavy ions of double-gate (DG) transistors is evaluated by numerical simulation and extensively compared with the response of single-gate (SG) partially-depleted and fully-depleted SOI devices. The study of bipolar amplification versus LET and track location shows that DG are less sensitive than SG with similar structure parameters. Moreover, in order to understand the downscaling impact on the DG sensitivity to heavy ions, the influence on the bipolar gain of various electrical and geometrical structure parameters is thoroughly analyzed.

Non‐linear performance comparison for FD and PD SOI MOSFETs based on the integral function method and Volterra modelling

AbstractThe harmonic and intermodulation distortions of both fully‐depleted (FD) and partially‐depleted (PD) silicon‐on‐insulator (SOI) MOSFETs are studied. The analysis is based on the recently developed integral function method and the results are compared to a third‐order Volterra model of the MOSFET. This modelling helps us to understand the non‐linear mechanisms of the considered devices and to predict their frequency behaviour. The models are validated through large‐signal network analyser measurements. The devices performances are discussed. Copyright © 2005 John Wiley & Sons, Ltd.

High frequency degradation of body-contacted PD SOI MOSFET output conductance

This paper analyses the frequency dependence of the output conductance (Gd) of several partially depleted (PD) SOI MOSFETs from the 0.18 µm technology node. Our experimental data indicate that body-tied and dynamic-threshold MOS devices suffer from a strong Gd degradation around 1 GHz. We propose a small signal interpretation and an equivalent circuit of the devices seen from the drain terminal to explain the observed phenomena. The model clearly identifies the non-zero value of the body resistance as the source of the Gd degradation.

On the great potential of non-doped MOSFETs for analog applications in partially-depleted SOI CMOS process

In this paper we discuss the potential applicability of SOI MOS transistors with non-doped (or intrinsic) channels for analog applications. We present the comparison of doped and intrinsic nMOSFETs in terms of parameters of the importance for analog designers and demonstrate that intrinsic devices are very promising for low-voltage, low-power analog applications, as they feature better threshold voltage control and predictability, higher maximum transconductance, driving current and attenuation of floating-body effects. We show that the use of non-doped devices gives the opportunity to create fully-depleted (FD) devices within a partially-depleted (PD) process. A new effect occurring in such intrinsic devices, which we call “PD-to-FD jump”, is described for the first time.

Noise performance of 0.35-/spl mu/m SOI CMOS devices and micropower preamplifier following 63-MeV, 1-mrad (Si) proton irradiation

Total dose and single-event radiation hardness, and operation over extreme temperatures make silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) processes leading contenders for space applications. This paper reports noise degradation of 0.35-/spl mu/m partially-depleted SOI CMOS devices and a micropower, low-noise preamplifier following 63-MeV proton irradiation to 1Mrad (Si). Proton irradiation, relevant for space mission environments, was considered since it induces both ionizing and displacement damage. Preamplifier input-referred white-noise voltage was minimized at low power consumption by operating input devices in moderate inversion for high transconductance efficiency. Flicker-noise, important for gyros and other mission sensors having low-frequency outputs, was minimized by large-area pMOS input devices and careful management of noninput devices. Measured 1-Hz gate-referred, flicker-noise voltage density increased 24 and 32% for pMOS and nMOS test devices respectively following 1 Mrad (Si) irradiation. Measured 1-Hz input-referred noise voltage density increased 22% between a nonirradiated and radiated preamplifier sample, which agrees closely with the 24% increase expected since noise is dominated by pMOS input devices. Device small-signal transconductance and white-noise were largely unchanged while output conductance appeared to increase over a factor-of-three. This suggests a modest design margin is required to maintain flicker noise performance, while substantial design margin may be required to maintain open-loop voltage gain.