Delay testing of partially depleted silicon-on-insulator (PD-SOI) circuits

Abstract

Partially depleted silicon-on-insulator (PD-SOI) technology has garnered more attention recently with regards to replacing traditional bulk-silicon technology as the mainstream technology of choice for high-performance/low-power digital applications. The increase in performance is due to the buried oxide layer, which provides a dramatic decrease in the source and drain junction capacitance, as well as a reduction in the traditional back biasing resulting from the body effect. The reported performance increases have been between 20% and 35%. However, this increase in performance comes at a cost of complexity from a performance measurement and delay testing perspective. Where the SOI transistor is faster than the bulk transistor, there exists a variation in delay caused by threshold voltage shifts that must be accounted for during manufacturing test. This paper explores these issues and proposes new test techniques for this promising technology