Delay testing of PD-SOI circuits

Abstract

Partially depleted silicon-on-insulator (PD-SOI) technology is an appropriate fabrication process for high-performance/low-power VLSI designs. SOI provides circuits with smaller delay and dynamic power consumption. However performance enhances come along with increase in complexity of performance measurement and delay testing. Whereas the SOI transistors are faster than the bulks, there exists variation in delay caused by threshold voltage shifts that must be considered during the manufacturing test. This paper presents new scan elements to overcome difficulty of delay testing in PD-SOI circuits that its silicon area is comparable to other solutions.