Abstract
Testing Partially-Depleted Silicon-On-Insulator (PD-SOI) integrated circuits presents new challenges that were not concerns in previous bulk CMOS technologies. Gates are affected by a variation in delay based on threshold voltage fluctuations. The fluctuations are dependent on the switching history of the device and this poses a serious challenge with regard to testing delays. To ensure worst-case operation, pre-conditioning of the path is necessary prior to a delay test. This paper provides background on SOI device operation and describes why and how pre-conditioning is accomplished. It is shown that a three-pattern delay test where the V1 and V3 patterns are the same is required to pre-condition the path for worst-case delay. Two novel scan latch designs that are capable of applying the three-pattern tests are presented.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
