Boxes: An Engineering Methodology for Calculating Soft Error Rates in SOI Integrated Circuits

Abstract

A simple methodology is necessary to characterize the SEU behavior of large quantities of RAM cell types, latches, flip-flops, other logic cells, I/O cells, etc. Such a methodology, called "Boxes", is being used for the Honeywell S150 radiation-hard 0.15 mum partially-depleted SOI process. Using physics-based equations, this paper shows how to break up each critical transistor into several "boxes", each with its own dimensions and critical charge, for the purpose of calculating soft error rate (SER). The Boxes methodology also allows for calculation of SER due to an ion that must simultaneously strike two separated sensitive volumes in order to cause an upset. This can be the dominant upset mechanism for many types of cells such as certain hardened SRAM's and other cells that obtain radiation hardness via extra transistors (such as triple modular redundancy, the DICE latch, etc.). Boxes also predicts upsets that can occur when an ion strike pulls a circuit node below ground or above the positive power supply. The boxes methodology was applied to a 6 T non-hardened SRAM, a hardened SRAM, and a D-type flip-flop. The theoretical predictions correlated well with experimental vertical ion strike data