Abstract

Aging and soft errors have become the two most critical reliability issues for nano-scale CMOS circuit. First, in this paper, the aging effect due to bias temperature instability (BTI) is analyzed on different logic gate using 45nm Technology, and simulated the critical charge and delay which can influence soft error rate (SER) result. Second, a method of SER calculation considering BTI effect is given. As a result, we find that the effect of PBTI on the circuit is less than that of NBTI on the critical charge. The critical charge and delay affect the masking effect and the probability of an error in SER calculation. Experimental result shows that the SER calculation considering BTI effect is feasible and the impact of BTI on benchmark circuit's SER is up to 21.6%.

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