Abstract
Under nano-scaled technology, the Integrated Circuit (IC) reliability issues caused by both aging mechanism and soft error become very critical. In this paper, from critical charge and delay points of view, the effects of Bias Temperature Instability (BTI), including Negative BTI (NBTI) and Positive BTI (PBTI), on Soft Error Rate (SER) are analyzed. Firstly, how BTI affects critical charge and delay is focused on. The delay increasing model is derived, and the critical charge changing procedure is introduced. Further, using the derived SER computational model considering critical charge, and mapping the changed delay into electrical mask procedure, the SER is accurately calculated. Experimental results on ISCAS89 benchmark circuits show that, considering two factors of BTI, SER estimation has high accuracy.
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