An Area-Efficient Design of Enhanced Space-Time Redundant DFF (IEST_TMR DFF)

Abstract

In the Application Specific Integrated Circuit (ASIC) design of spacecraft, anti-radiation performance is a very important factor, and Triple Modular Redundancy (TMR) is a common radiation hardened method, which can well resist the Single Event Upset (SEU) in sequential units. However, conventional TMR cannot eliminate Single Event Transient (SET) pulses that occur in combinational logic. So, varieties of improved schemes have been proposed, including the Space-Time TMR (ST_TMR), the Enhanced Space-Time TMR (EST_TMR), and TMR_5DFF. However, ST_TMR and EST_TMR will cause timing errors in specific cases, and the area cost of TMR_5DFF is too large. Therefore, this paper proposes an area-efficient Improved Enhanced Space-Time TMR (IEST_TMR) scheme based on EST_TMR, which can not only solve the timing errors of EST_TMR, but also reduce the area cost compared with TMR_5DFF. In order to verify the validity of IEST_TMR, this paper uses the Soft Error Rate (SER) analysis method based on double exponential current source and the C17 circuit in ISCAS'85 as the test circuit to analyze the SER of the circuit using IEST_TMR DFF. In addition, we implement a simple anti-radiation Universal Asynchronous Receiver/Transmitter (UART) module by using the method of the Second Synthesis of Modified Netlist (SSMN), and further verify the validity of the IEST_TMR DFF by injecting faults in the back-end simulation.