Radiation Hardened Design Based on TMR_5DFF for ASIC

Abstract

In the design of Application Specific Integrated Circuit (ASIC) chips, Triple Modular Redundancy (TMR) is a commonly used technology to effectively improve the chip's capability of resisting the Single Event Upset (SEU), but can’t mask transient faults caused by SEU in the combination circuit. The Space-Time TMR (ST_TMR) and the Enhanced Space-Time TMR (EST_TMR) can solve the above problem, but the former and latter two-stage latches that make up EST_TMR can be turned on at the same time. In response to this problem, this paper proposes a new EST_TMR-TMR_5DFF. TMR_5DFF is triggered by the edge of the clock by replacing the latches of the EST_TMR with flip-flops, which solves the problem that the two-stage latches of the EST_TMR are turned on at the same time. In order to verify the validity of the proposed TMR_5DFF structure, this paper implements a simple anti-radiation Universal Asynchronous Receiver/Transmitter (UART) circuit by using the method of the Second Synthesis of Modified Netlist (SSMN). In addition, we perform fault injection on the UART circuit with the TMR_5DFF structure and analyzed the simulation results. The TMR_5DFF can well solve the problem that the two-stage latches of the EST_TMR are turned on at the same time and can be used more widely in the anti-radiation circuit design.