Parasitic Inductance Research Articles

Utilizing Mutual Coupling to Eliminate Parasitic Inductance in EMI Filter Capacitors for Noise Reduction

Utilizing Mutual Coupling to Eliminate Parasitic Inductance in EMI Filter Capacitors for Noise Reduction

A 2.5D Multichip SiC MOSFET Power Module With Low Parasitic Inductance and High Dynamic Current Sharing Performance

A 2.5D Multichip SiC MOSFET Power Module With Low Parasitic Inductance and High Dynamic Current Sharing Performance

An Informetric View to the Negative Capacitance Phenomenon at Interlayered Metal-Semiconductor Structures and Distinct Electronic Devices

Negative Capacitance (NC) phenomenon, which can be explained as the material exhibiting an inductive behavior, is often referred to as "anomalous" or "abnormal" in the literature. Especially in the forward bias/deposition region, the presence of surface states (Nss) and their relaxation times (τ), series resistance (Rs), minority carrier injection, interface charge loss in occupied states under the Fermi energy level, parasitic inductance, or poor measuring equipment calibration problems can be counted among the causes of this phenomenon. Studies on NC behavior have shown that this behavior can be observed for different frequencies, temperatures, and related parameters at forward biases. However, the NC behavior, which appears as an unidentified peak in admittance spectroscopy data, is not yet fully understood. Ultimately, this study aims to compile and analyze the NC reported in selected scientific studies, investigate the source of this phenomenon, and observe statistics in a general view.

Investigation of a Low-Speed Commutation Voltage Shock Problem in Three-Level ANPC Inverter with Hybrid Modulation Mode

With the development of the photovoltaic industry; there will be an increasing demand for efficient, high-power density, and low-cost grid interface converters. Compared with two-level inverters, multilevel inverters have the following advantages: (1) lower device voltage ratings; (2) better output filtering spectrum; (3) lower electromagnetic interference (EMI) noise; and (4) higher switching speed capability. However, the complex switching circuit of the multilevel inverter will bring more parasitic inductance, resulting in severe switching overvoltage (ringing). Especially in order to reduce the cost of the inverter, using the long-loop modulation mode, the commutation loop will introduce more parasitic inductance, which will make the overvoltage more serious. Consider that commonly used overvoltage absorption schemes are effective only for overvoltage or suppression of oscillations. Therefore, a new overvoltage absorption circuit is proposed in this paper, which can not only alleviate the overvoltage and ringing phenomena but also suppress the effect of voltage jumps during low-frequency switching on high-frequency input voltage. This overvoltage absorption circuit is characterized by low overvoltage, fast ringing damping, and minimum capacitance. Experiments and simulations are conducted to verify the effectiveness of this overvoltage absorption circuit using a three-level ANPC inverter as a prototype. The results show that the proposed overvoltage absorption circuit can significantly reduce the overvoltage level, shorten the oscillation time, and reduce the voltage difference between the upper and lower DC bus capacitors.

Mechanism of gate voltage spike under digital gate control at IGBT switching operations

This paper reports the mechanism of gate voltage spike in the turn-off operation by a digital gate control. In the previous work, it was clarified that the gate voltage spike Vg_spike was generated by parasitic inductance and a large gate current change due to the digital gate control. However, the main cause of resonance leading to Vg_spike generation has never been clear. Three types of IGBT modules, which have the same gate inductance and different input capacitance, were tested under three-step digital gate control. It was found that the Vg_spike was independent of input capacitance in IGBT. As for the stray capacitance in the digital gate driver, external capacitors Cex were connected in parallel with the gate driver, and the Vg_spike decreased with increasing Cex. Furthermore, the second vector of the digital control, which was applied for suppressing the overshoot in collector-emitter voltage by a small value, needed to be set as a large value to suppress the Vg_spike. From these results, output impedance of gate driver is a key factor for the Vg_spike, and the second vector must be optimized for not only the collector voltage overshoot but also Vg_spike suppression for safety operation.

A new soft‐switching high gain DC/DC converter with bipolar outputs

AbstractThis paper introduces a new single‐input multi‐output step‐up DC/DC converter with soft‐switching performance and low input current for renewable energy applications. The proposed topology uses a three‐winding coupled‐inductor (TWCI) and voltage multiplier circuits to achieve high voltage gains. The bipolar output voltages of the proposed converter can be varied independently by tuning the turns ratios of the TWCI. Due to the semi‐trans‐inverse specification of the suggested topology, high voltage gains can be obtained under a lower number of turns ratio in the magnetic device. Furthermore, a regenerative passive clamp technique mitigates the voltage stress on the single power switch. Additionally, the power dissipations are further reduced by considering a resonant tank in the circuit. In the converter, the parasitic leakage inductances of the TWCI windings help to provide the soft‐switching conditions for the switch and also to eliminate the reverse‐recovery loss for all converter diodes. The operating mode of the presented converter has been introduced and the steady state, along with the main operating equations have also been derived. Finally, the theoretical analysis is verified by a sample prototype 235 W at the input voltage 25 V and outputs of 200 V and −200 V.

Energy Extraction System for the Superconductive Solenoid with Current 5100 A and Stored Energy 22 MJ

At the FAIR (Facility for Antiproton and Ion Research, Darmstadt, Germany) accelerator complex under construction, one of the key experiments is the PANDA experiment. The main field of the PANDA spectrometer is provided by a superconducting solenoid. The energy of the magnetic field stored in a superconducting solenoid reaches 22 MJ at an operating current of 5100 A. In the case of the transition of the superconducting cable used for the solenoid winding into a resistive state, the safe extraction of stored energy is required to protect the magnet. The energy extraction system proposed by the authors provides energy dissipation inside the external dump resistor, and not in the section of the superconducting cable that has passed into resistive state, while preventing its damage. The most critical elements of the energy extraction system are the current breaker, with the help of which the dump resistor is introduced into the power circuit of the superconducting solenoid, and the dump resistor itself. A modernized three-phase circuit breaker was chosen as current breaker. A unique design of the energy extraction system including dump resistor with a low parasitic inductance has been developed.

Modelling and mitigating oscillation in E-mode GaN HEMT: A simulation-based approach to parasitic inductance optimization

The escalating demands in energy conversion necessitate the evolution of efficient power electronic devices beyond the limitations of traditional silicon (Si) counterparts. This research delves into the intricacies of the Enhancement mode Gallium Nitride High Electron Mobility Transistor (E-mode GaN HEMT). A focus is placed on its static characterization, parameter analysis, and the influence of external parasitic inductances, particularly regarding oscillation challenges during its hard switching process. Forward and revise bias are conducted through comparison with Si-MOSFET and Cascade-GaN HEMT, along with its static on-resistance and transfer characteristics. Through rigorous half-bridge double pulse circuit LTSPICE simulations, this study deciphers the turn-on and turn-off dynamics of the E-mode GaN HEMT. By scrutinizing various parasitic inductances, the research elucidates mechanisms instigating high-frequency voltage and current oscillations. Significantly, the research presents a hierarchy of parasitic inductance influences, employing an energy loss comparison. This analysis underscores the prominent impact of the common source parasitic inductance, which exhibits energy loss increases of 23.6 % and 22.7 % at junction temperatures of 25 °C and 75 °C, respectively. Building on these insights, the study recommends strategies to mitigate the effects of external parasitic inductance, underscoring the pivotal role of oscillation suppression in advanced GaN Printed Circuit Board (PCB) and Integrated Circuit (IC) designs. This comprehensive inquiry provides a blueprint for enhancing GaN circuit designs, paving the way for their optimal application in the evolving realm of power electronics.

Current imbalance analysis of multichip influenced by parasitic inductance within PP-IEGT

The Press-Pack Injection Enhanced Gate Transistor (PP-IEGT) technology is frequently employed in converters for high power systems. In the device packaging, the imbalanced current sharing among chips has become a significant issue for device reliability. Considering the semiconductor structure of IEGT is different from the conventional power devices, the main prerequisite for fully quantifying the current distribution is to establish a suitable electrical model for IEGT. Thus, this paper proposes an IEGT single chip lumped-charge model taking into account the effect of carrier injection enhancement in the emitter. Furthermore, as for the parallel branches in PP-IEGT, the parasitic inductance of the drive board and pillars within the package are extracted by Ansys simulation, and the validity of Ansys simulation is verified by the port S-parameter method. Finally, combining the electrical model and the effect of mutual inductance, the switching inconsistency is evaluated. It is demonstrated that the farther the branch from the gate inlet, the greater the gate inductance withstands. Besides, the mutual inductance is an important factor to influence the electrical parameter distribution. Both mutual coupling coefficient and current density display degressive trends with the increases of the gap between parallel chips.

An Ameliorated Small-Signal Model Parameter Extraction Method for GaN HEMTs up to 110 GHz with Short-Test Structure

An improved method of extracting small-signal equivalent circuit model parameters for gallium nitride high electron mobility transistors (GaN HEMTs) is presented. This paper intends to present a method to extract the parasitic inductance and resistance of transistors based on the short-test structure without the open-circuit test structure. The parasitic capacitance of transistors is extracted by the method based on the size scalable model. Compared with the traditional COLD-FET method, the extraction procedure is simpler and more convenient. After removing the influence of parasitic elements, the intrinsic parameters of the model can be extracted by the S-parameters measured at different bias points. The experimental results show that the simulation results have good agreement with the measured results in the range of 0.5∼110 GHz.

A failure mechanism of IGBT module in MMC and improvement

In modular multi-level converter valves, as the blocked mode happens, the failure in IGBT modules often causes a chain explosion reaction, which masks the initial failure mechanism. The root cause of the failure was that the voltage, consisting of the diode forward voltage and the induced voltage on the parasitic inductance, exceeded the reverse blocking capability of the anti-parallel IGBT. The methods against the failure were studied from three aspects: decreasing the diode’s peak forward voltage, increasing the reverse blocking capability of IGBT, and minimizing the parasitic inductance of the package. It was found that the doping concentration’s effect on the diode’s peak forward voltage is not monotonic. It can be explained from the carrier density distribution during forward recovery transient that lower doping concentration reduces the carrier injection, and higher doping concentration reduces the excess carrier concentration in the doping region. Then, the influence of two buffer designs on the reverse blocking capability of IGBT was compared. It was found that a higher reverse blocking voltage would be achieved when a multi-proton implantation buffer replaced the diffused buffer. And the new design has almost no degradation in forward blocking capability.

Evaluation of antiparallel SiC Schottky diode in SiC MOSFET phase-leg configuration of synchronous rectifier

The MOSFET synchronous rectification (SR) is widely used to reduce the conduction loss during the freewheeling period. Due to the wide band gap of silicon carbide (SiC), the intrinsic body diode of SiC MOSFET exhibits a high voltage drop. Therefore, SiC Schottky diodes (SBD) and SiC MOSFETs are usually used in reverse parallel to reduce power loss. However, the increase of equivalent junction capacitance due to the addition of an external SiC SBD could bring larger turn-on current on opposite power transistor of the phase-leg. Furthermore, as the parasitic inductance associated with layout hinders the prompt transfer of current between SiC SBD and body diode, the external SiC SBD cannot be fully utilized, and it may deteriorate the overall performance, especially at heavy load. We comprehensively compare power losses when SiC SBD are antiparallel or not, at different working conditions, including different layout compactness, load current and dead time. It’s hard to get the effect of loss reduction loss when add antiparallel SiC SBD due to the parasitic inductance induced by the layout. The results can provide a guidance to properly select SiC SBD in a phase-leg configuration under SR mode for freewheeling during the dead time.

Bond wire lift-off detection by gate voltage waveform in IGBT turn-off process enhanced by digital gate control

This paper presents a new detection method of bond wire lift-off in Insulated Gate Bipolar Transistor (IGBT) power module. The bond wire lift-off is a major failure mode in power cycle degradation of the IGBT module, and many monitoring methods have been proposed and demonstrated for safety operation of power electronics systems in the previous works. In this study, we focus on the gate voltage waveform as an indicator to detect wire-lift for a simple and straightforward detection method. Due to the increase in parasitic inductance caused by bond wire lift-off, the turn-off switching waveform becomes modulated. The digital gate control (DGC) was employed to control the switching behavior to obtain precision for low-noise and high-performance. Furthermore, the DGC 2-step vector control (2-sVC) can enhance the sensitivity of bond wire lift-off failure detection by gate voltage waveform change. As feature quantities, the gate voltage spike peak, its amplitude and the timing shift were measured at various operating conditions. The DGC obtained larger feature quantities compared with conventional gate control. In particular, high-current conditions were found to be more favorable for achieving high sensitivity due to the high die/dt. From these results, the DGC is effective to achieve both the high sensitivity to detect bond wire lift-off by gate voltage waveform and maintaining the best switching performance.

Study of different parameters influencing IGBT and diode robustness under short-circuit type III conditions

The purpose of this work is to study the influence of different parameters on short-circuit type III (SC-III) robustness limit of the IGBT and freewheeling diodes (FWD) beyond the specified datasheet values. SC-III measurements without gate-emitter voltage (VGE) clamping show a reduced SC-III safe operating area (SOA) at higher DC-link voltages because of high collector current peaks (IC,peak) induced by transient gate-emitter overvoltage and subsequent high negative diC/dt values. By applying a VGE clamping circuit, SC-III last-pass collector-current (IC,sat,Lastpass) can be fully recovered to the level of SC-I, even though the IGBT and diode encounter harder conditions in the SC-III event. Parameters such as parasitic inductance (Lpar), load current (Iload) and temperature (Tstart) have an influence on the SC-III robustness limit of the IGBTs and FWDs. Also, the second reverse-recovery peak of the FWD during an SC-III event is strongly influenced by whether the gate-emitter voltage is applied across the sense or load-emitter terminal.

Investigation of Surge Voltage Propagation in Inverter-Driven Electric Machine Windings

This paper investigates what parameters affect the voltage propagation pattern in inverter-driven electric machine windings and presents mathematical analysis of this pattern with experiment verification. This work provides a thorough understanding of the behavior of machine windings under surge voltage excitations. First, high-fidelity finite element (FE) models were constructed with various combinations of factors in random-wound stranded machine windings. These factors include various types of parasitic capacitances, parasitic inductances of parallel strands and different wire layouts in slots. The surge voltage distribution along the windings was simulated and compared among different cases to identify the key factors that affect this voltage propagation pattern. Subsequently, machine windings with both single-phase and three-phase structures were analyzed via equivalent circuits that were constructed with those key parameters. Then, the expressions of the coil voltage were derived in the Laplace domain. These expressions explicate the uneven surge voltage propagation pattern at various frequencies. Finally, for verification, both simulations and tests were conducted to analyze the surge voltage propagation in single-phase and three-phase windings.

Suppression of Simultaneous Switching Noise Using Embedded Capacitor Method in High-Speed Systems

Gbps signals are commonly used in modern high-speed IO designs. These systems require a high level of signal accuracy. However, these signals can cause current fluctuations at high frequencies due to parasitic inductance on the package and board, leading to significant changes in supply voltage. DDRX interfaces that transmit data up to 4.8 Gbps induce simultaneous switching noise (SSN) in the voltage regulator module (VRM). One of the adverse effects of SSN is timing jitter, also known as power supply-induced jitter. The amount of SSN is directly proportional to the number of signals on a parallel bus. Discrete capacitors may not be effective in reducing SSN impact when data is transmitted at high speeds. The current approach used to predict and evaluate errors in SSNs relies on the designer's expertise, which requires accurate estimates of packaging parasitic. In this paper, a practical approach to lessen SSN is presented through the use of embedded capacitors placed between planes and optimizing discrete capacitors by connecting them in a way that measures the impact of supply noise on the I/O transistor circuit performance at the DDRX interface. Two boards were designed, evaluated, and subsequently compared their results.

Low Inductive Characterization of Fast-Switching SiC MOSFETs and Active Gate Driver Units

Accurate switching device characterization is necessary for effectively utilizing the technological ad-vantages of Silicon Carbide (SiC) Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) over their Silicon (Si) Insulated-Gate Bipolar Transistor (IGBT) counterparts. With switching times of few nanoseconds, the unprecedented switching speed of SiC semiconductor devices challenges today's converter and characterization setup designs in regard to parasitic layout inductances for optimal conversion and reliable characterization data. Fur-thermore, active gate driving is a key to unlock the potential of SiC MOSFETs, but requires performance assessment prior to integration. This paper presents a low-inductive test platform for flexible and high-accuracy characterization of fast-switching SiC MOSFETs and active gate drivers evalu-ation. The test circuit delivers high quality characterization data that is comparable with a commercial dynamic power device characterizer. In addition to the conventional hard-switching double-pulse tests with a two-level voltage source gate driver, the test circuit offers soft-switching and gate driver evaluation capability in addition. This test platform is a valuable tool for obtaining reliable characterization data to develop more accurate SiC MOSFET simulation models, and evaluate the combination of gate driver and MOSFET prior to the prototyping phase of a converter.

A Cascaded Modular Isolated Back-to-Back Solid State Transformer Scheme for AC/DC/AC Interconnection With Improved Performance and Simple Control

This paper proposes a cascaded modular isolated back-to-back solid-state transformer (CMIB-SST) for electrical isolated interconnection of two distribution AC grids, which consists of modular multilevel converter (MMC)-stage, cascaded H bridge (CHB)-stage, and six-terminal active bridge (STAB)-stage. A switching synchronization hybrid phase-shift modulation (SSHPSM) for the STAB-stage is utilized to suppress the low-frequency voltage ripple of submodule (SM) both in CHB-stage and MMC-stage to reduce the SM capacitance significantly with a simple control scheme of the CMIB-SST. The proposed CMIB-SST is friendly to the cost under the new capacitance constraint, and the big size electrolytic capacitor could be replaced by film capacitor, which is beneficial to security and life of the SST module. The voltage gain, mathematical model of the proposed SST is analyzed to illustrate the principle of SM low-frequency ripple-current decoupling with the SM capacitor and cancellation mechanism in STAB-stage. The corresponding transformer design are carried out under considering the parasitic leakage inductance value and the constraints of its magnetic fields, thermal, electric field strength and insulation. The scheme is evaluated by cost and volume of switches, SM capacitors and magnetic unit. Finally, the processed topology and SSHPSM method are verified by simulation and experimental results.

Simulation And Design of a Vertical Gallium Nitride JFET with Dual Lateral Heterojunction Channels

A novel vertical gallium nitride (GaN) junction field-effect transistor (JFET) is reported in this article. Through the setup of dual lateral heterojunction channels in the body, the current density is high while the p-type gallium nitride growth area can be adjusted to easily achieve enhanced mode. Based on the structure parameter settings in this article, through the device simulation software TCAD, and under the condition of selecting the appropriate p-type GaN growth region, the threshold voltage of the device is 1.1 V, the source output current density can reach 7.2 kA/cm2, the breakdown voltage is about 750 V, and the on-resistance is 0.52 mΩ·cm2. Finally, the test circuit is built, and the switching characteristics of the device proposed in this paper are simulated under the consideration of parasitic inductance.

A Multitime-Scale Analytical Model of ZVS Buck Converter

This paper presents a modeling method to build the complete and accurate multi-time-scale analytical model for low-voltage eGaN HEMTs based zero voltage switching (ZVS) Buck converter with consideration of parasitic inductors, nonlinear junction capacitors and nonlinear transconductance, etc. The switching steady-state modes and switching transient modes are discussed in detail based on their corresponding equivalent circuits. The state equations of each mode are solved by MATLAB software to obtain the key operating waveforms throughout one switching cycle. Moreover, the established switching steady-state model and switching transient model are numerically merged together through continuous state variables, and then the multi-time-scale model for stable operation is formed based on the iterative method. The waveforms and switching energy losses predicted by the model within one switching cycle are compared with the experimental results, respectively, to verify the accuracy of the model. In the end, the dead time is optimized based on the proposed model, and the optimization result is verified to be effective in reducing the switching energy loss through experiment.