Current imbalance analysis of multichip influenced by parasitic inductance within PP-IEGT

Abstract

The Press-Pack Injection Enhanced Gate Transistor (PP-IEGT) technology is frequently employed in converters for high power systems. In the device packaging, the imbalanced current sharing among chips has become a significant issue for device reliability. Considering the semiconductor structure of IEGT is different from the conventional power devices, the main prerequisite for fully quantifying the current distribution is to establish a suitable electrical model for IEGT. Thus, this paper proposes an IEGT single chip lumped-charge model taking into account the effect of carrier injection enhancement in the emitter. Furthermore, as for the parallel branches in PP-IEGT, the parasitic inductance of the drive board and pillars within the package are extracted by Ansys simulation, and the validity of Ansys simulation is verified by the port S-parameter method. Finally, combining the electrical model and the effect of mutual inductance, the switching inconsistency is evaluated. It is demonstrated that the farther the branch from the gate inlet, the greater the gate inductance withstands. Besides, the mutual inductance is an important factor to influence the electrical parameter distribution. Both mutual coupling coefficient and current density display degressive trends with the increases of the gap between parallel chips.