Parasitic Bipolar Effect Research Articles

Pulsed measurements and circuit modeling of weak and strong avalanche effects in GaAs MESFETs and HEMTs

An extensive characterization of the on-state breakdown characteristics of GaAs based MESFETs and HEMTs has been carried out by means of DC and pulsed measurements and of circuit simulations. A computer-controlled, three-terminal Transmission Line Pulse (TLP) system with 50-100 ns pulse width and sub-ns risetime has been developed, which allows automated pulsed measurements of device I-V characteristics. The TLP system has been adopted for nondestructive measurements of the on-state breakdown characteristics of GaAs MESFETs and HEMTs up to unprecedented values of gate current density (I/sub G//W=30 mA/mm has been reached), in strong avalanche conditions. The device behavior in strong avalanche conditions is dominated by a parasitic bipolar effect (PBE) similarly to SOI and bulk Si MOSFETs. By taking into account this and other parasitic effects, an equivalent circuit model, suitable for SPICE simulations has been developed. The proposed model is capable of predicting the exact behavior of the gate and drain currents in both weak and strong avalanche conditions.

Hot-carrier-induced degradation for partially depleted soi 0.25-0.1 μm CMOSFET with 2-nm thin gate oxide

Hot-carrier-induced degradation of partially depleted SOI CMOSFETs was investigated with respect to body-contact (BC-SOI) and floating-body (FB-SOI) for channel lengths ranging from 0.25 down to 0.1 /spl mu/m with 2 nm gate oxide. It is found that the valence-band electron tunneling is the main factor of device degradation for the SOI CMOSFET. In the FB-SOI nMOSFET, both the floating body effect (FBE) and the parasitic bipolar transistor effect (PBT) affect the hot-carrier-induced degradation of device characteristics. Without apparent FBE on pMOSFET, the worst hot-carrier stress condition of the 0.1 /spl mu/m FB-SOI pMOSFET is similar to that of the 0.1 /spl mu/m BC-SOI pMOSFET.

Low temperature operation of 0.13 μm Partially-Depleted SOI nMOSFETs with floating body

An extended low temperature study of 0.13μm Partially-Depleted Silicon-On-Insulator nMOSFETs without body contact is carried out. The impact of HALO doping characteristics on device output performance is investigated. The electrical properties of the technology are explored in terms of circuit applications both in digital and analog sense. The occurrence of inherent parasitic bipolar effects is also studied.

Suppression of Parasitic BJT Action in Single Pocket Thin Film Deep Sub-Micron SOI MOSFETs.

AbstractA study of parasitic bipolar junction transistor effects in single pocket thin film siliconon-insulators (SOI) nMOSFETs has been carried out. Characterization and simulation results show that parasitic bipolar junction transistor action is reduced in single pocket SOI MOSFETs in comparison to homogeneously doped conventional SOI MOSFETs. A novel Gate-Induced-Drain-Leakage (GIDL) current technique was used to characterize the SOI MOSFETs. 2 - D simulations were carried out to analyze the reduced parasitic bipolar junction effect in single pocket thin film SOI MOSFETs.

SOI MOSFET structure with a junction-type body contact for suppression of pass gate leakage

A SOI MOSFET structure with a junction-type body contact [body-junctioned-to-gate (BJG)] is proposed to effectively suppress the parasitic bipolar effect in all kinds of MOSFETs including the pass transistor, which can be realized with compact design and simple processes. It utilizes the buried contact process to minimize the area consumption. Various on-chip test circuits have been fabricated to verify the BJG characteristics and it is shown that the proposed structure provides nearly perfect immunity against the circuit failure caused by the parasitic bipolar effect and an excellent speed performance, so that it can be a promising candidate for the SOI circuits.

Breakdown quenching in high electron mobility transistor by using body contact

In this paper, the effect of a body contact (BC) to quench breakdown effects and increase the breakdown voltage in high-electron mobility transistors (HEMTs) is theoretically investigated. The body contact is formed by a highly p-type doped substrate connected to an ohmic back contact. By means of a two-dimensional (2-D) self consistent Monte Carlo simulator we show that the BC prevents holes generated by impact ionization (II) from accumulating in the channel and in the buffer, thus inhibiting the parasitic bipolar effect (PBE). This improves the breakdown behavior and extends the range of the usable drain voltages.

Graded-channel fully depleted Silicon-On-Insulator nMOSFET for reducing the parasitic bipolar effects

An extended study of the occurrence of inherent parasitic bipolar effects in conventional and graded-channel fully depleted silicon-on-insulator nMOSFETs is carried out. The graded-channel device is a new asymmetric channel MOSFET, fabricated through a simple process variation. Measurements and two-dimensional simulations are used to demonstrate that the graded-channel device efficiently alleviates the parasitic BJT action, improving the breakdown voltage, by the reduction of impact ionization in the high electric field region. Based on process/device simulation and modeling, multiplication factor and parasitic bipolar gain, which are the responsible parameters for the parasitic BJT action, are investigated separately providing a physical explanation. The abnormal subthreshold slope and hysteresis phenomenon are also studied and compared.

Monte Carlo study of the dynamic breakdown effects in HEMT's

We present a theoretical investigation of the near-breakdown scenario in pseudomorphic high electron mobility transistors (HEMT's). We show that the main mechanism for the enhanced drain current is a parasitic bipolar effect due to holes, generated by impact ionization, which accumulate in the channel and in the substrate close to the source contact. The dynamic of this charge accumulation and of the consequent drain current increase is studied by means of a two-dimensional (2-D) Poisson Monte Carlo simulator.

FACTORS LIMITING THE MAXIMUM OPERATING VOLTAGE OF MICROWAVE DEVICES

The operating voltage of advanced microwave devices is currently limited by impact-ionization and breakdown effects. An extended study of the effects of hot carriers on the breakdown behavior and reliability of GaAs-based and InP-based HEMTs (high electron mobility transistors) has been carried out by means of pulsed measurements, electroluminescence spectroscopy and microscopy and Monte Carlo simulations. We show that the parasitic bipolar effect, which explains kink effects in HEMTs, can also induce regenerative phenomena eventually leading to on-state breakdown. Results concerning the effects of hot carrier aging on GaAs-based and InP-based HEMTs are summarized.

Factors Limiting the Maximum Operating Voltage of Microwave Devices

The operating voltage of advanced microwave devices is currently limited by impact-ionization and breakdown effects. An extended study of the effects of hot carriers on the breakdown behavior and reliability of GaAs-based and InP-based HEMTs (high electron mobility transistors) has been carried out by means of pulsed measurements, electroluminescence spectroscopy and microscopy and Monte Carlo simulations. We show that the parasitic bipolar effect, which explains kink effects in HEMTs, can also induce regenerative phenomena eventually leading to on-state breakdown. Results concerning the effects of hot carrier aging on GaAs-based and InP-based HEMTs are summarized.

Monte Carlo simulation of impact ionization and light emission in pseudomorphic HEMTs

We present theoretical investigations of electrical and optical phenomena in the near breakdown regime of pseudomorphic HEMTs. The main effect of the drain current enhancement is found to be a parasitic bipolar effect due to holes, created by impact ionization, which accumulate in the substrate. Calculated electroluminescense spectra of holes, radiatively recombining with electrons in the source-sided channel, exhibit transitions which are allowed due to the bias-induced band bending of the channel. The calculated electroluminescence of the gate-source region agrees well with available experimental data. We predict that the hole accumulation in the source side of the channel region takes place on a time scale of ∼150 ps, thus allowing a direct time-resolved experimental observation.

Analytical threshold voltage model for ultrathin SOI MOSFETs including short-channel and floating-body effects

Short-channel effects (SCE) in ultrathin silicon-on-insulator (SOI) fully depleted (FD) MOSFETs are analyzed and an analytical model for threshold voltage, including the kink effect, is presented. The proposed model accounts for (1) a general nonuniform channel doping profile, (2) the drain-induced V/sub th/- lowering enhancement resulting from the interaction of (a) impact ionization, (b) floating-body, and (c) parasitic-bipolar effects. Good agreement between the proposed model and experimental data is demonstrated. Impact ionization and floating-body effects dominate V/sub th/ lowering for drain voltages larger than V/sub dk//spl sime/B/sub i/./spl lambda//sub i//3, where B/sub i/ is the impact ionization coefficient, and /spl lambda//sub i/ is the impact ionization length, a structural parameter which, for a single-drain SOI MOSFET, coincides with the SCE characteristic length /spl lambda/.

Dual-mode parasitic bipolar effect in dynamic CVSL XOR circuit with floating-body partially depleted SOI devices

This paper presents a detailed study on the impact of the floating body in a partially depleted (PD) SOI MOSFET on a multi-level voltage-switch current-steering type circuit using the dynamic CVSL XOR circuit as an example. It is shown that because of the cascading, differential input configuration, symmetry, and crisscross drain connections in the circuit topology, both normal-mode and inversemode parasitic bipolar effect (with parasitic bipolar current flowing from the source to the drain) will be present in every cycle when the clock changes from the precharge phase to the evaluation phase. The resulting impact on the circuit operation, stability and functionality is studied. The normal-mode parasitic bipolar effect is shown to lead potentially to an erroneous logic state. The history dependency (hysteresis) and pattern dependency of the parasitic bipolar effect are discussed.

An Asymmetric Channel SOI nMOSFET for Reducing Parasitic Effects and Improving Output Characteristics

A device based on an asymmetric channel doping profile with the aim of reducing the inherent parasitic bipolar effects in fully depleted silicon-on-insulator (SOI) devices and improving the output characteristics is introduced. Measurements and two-dimensional simulations are used to study the device capabilities and limitations. (C) 1999 The Electrochemical Society. S1099-0062(99)07-087-X. All rights reserved.

Improving the Characteristics of Ultra-Thin-Film Fully-Depleted Metal-Oxide-Semiconductor Field Effect Transistors on SIMOX (Separation by IMplanted OXygen) by Selective Tungsten Deposition on Source and Drain Region

Selective tungsten (W) chemical-vapor-deposition (CVD) with hydrogenation and hydrogen-termination (HHT) is applied to ultra-thin-film fully-depleted (FD) metal-oxide-semiconductor field effect transistors (MOSFETs) on SIMOX (Separation by IMplanted OXygen) for reducing the sheet resistance of source and drain regions. 0.25-µm-gate MOSFETs on SIMOX (MOSFETs/SIMOX) with a top Si layer with a thickness of 50 nm are fabricated using selective W-CVD, and their characteristics, including hot-carrier effects and latch-onset voltage, are systematically investigated. It is found that selective W-CVD with HHT can reduce the source/drain (S/D) sheet resistance in 50-nm-thick ultra-thin-film SIMOX to 10 Ω/sq. or less. This ensures that W deposition increases the drain saturation current. It is also found that W deposition largely suppresses the parasitic bipolar effects. Consequently, the anomalous subthreshold slope diminishes, hot carrier reliability improves, and the latch-onset voltage rises to over 2.5 V. Moreover, it is clarified that the parasitic bipolar effects are largely suppressed when the W layer is within 0.3 µm from the source/body junction. This is because W effectively extracts the holes generated by impact ionization, and thus suppresses the accumulation of holes which would otherwise induce an increase in the body potential.

30.4: Short‐Channel Effect of Sub‐Micron Poly‐Si TFTs with Large Poly‐Si Grains

AbstractTo study 3 V‐driven LSI‐like TFTs, we fabricated high‐temperature n‐channel poly‐Si TFTs, some of which had a subthreshold slope of 90 mV/dec and an electron field mobility of 432 cm2/Vs, with submicron channel length and large poly‐Si grains. We only observed an anomalous parasitic bipolar transistor effect in the TFTs with good trans‐conductance, and concluded that the grain‐boundary affects the trans‐conductance severely than the threshold voltage and the subthreshold slope.

Recombination Centers Created by Ar + ‐Ion Implantation into SIMOX Substrates

The characteristics of the defects created by ‐ion implantation into SIMOX substrates, to suppress the parasitic bipolar effect in a floating‐body n‐metal‐oxide‐semiconductor field effect transistor/SIMOX (n‐MOSFET/SIMOX) were investigated Secondary‐ion mass spectroscopy showed that implanted Ar atoms gathered in the top Si layer by annealing and their concentration decreased with increasing annealing temperature. No secondary defects were observed in the top Si layer by cross‐sectional transmission electron microscopy, when ions were implanted near the interface between the top Si layer and the buried oxide (BOX) layer. The implanted Ar atoms did not affect boron atoms, but they deactivated phosphorous atoms electrically. This deactivation is thought to form an argon‐phosphorous complex. Electron spin resonance measurements showed that the defects created in SIMOX substrates were paramagnetic defects called the Pb centers at the top‐Si/BOX interface. Therefore, it is concluded that an Ar atom itself does not form a recombination center and that the Pb centers created by implantation act as recombination centers preventing parasitic bipolar action in an n‐MOSFET/SIMOX.

Application of Reversed Silicon Wafer Direct Bonding to Thin-Film SOI Power ICs

Reversed silicon wafer direct bonding (RSDB) has been applied to Silicon-on-insulator (SOI) power Integrated Circuits (ICs). The RSDB power metal-oxide-semiconductor field-effect transistor (MOSFET) is superior to the power MOSFET using a conventional SOI substrate. In a RSDB power MOSFET, the threshold voltage is independent of the substrate bias because its gate electrode shields the substrate bias from the channel. Moreover, the parasitic bipolar effect is suppressed. RSDB also has a higher production yield. Two-dimensional device simulation results show how to optimize the device parameters enabling us to maximize the breakdown voltage of the RSDB power MOSFET. The electrical characteristics of nMOSFETs fabricated using RSDB are the same as those of nMOSFETs fabricated using the conventional SOI substrate.

Study on the device characteristics of a quasi-SOI power MOSFET fabricated by reversed silicon wafer direct bonding

The device characteristics of a quasi-SOI power MOSFET were investigated to obtain its optimum device structure. The oxide at the original bottom surface of the bulk power MOSFET of the quasi-SOI power MOSFET formed by reversed silicon wafer direct bonding acts as the buried oxide of the conventional SOI power MOSFET. The short channel effect of the quasi-SOI power MOSFET was larger than that in the conventional SOI power MOSFET. It was suppressed by increasing the width of the oxide in the body region, and the parasitic bipolar effect was suppressed by decreasing it. We also propose a new device structure which can suppress the short channel effect and parasitic bipolar effect of a quasi-SOI power MOSFET based on the results of these experiments.

Suppression of the floating-body effect in SOI MOSFET's by the bandgap engineering method using a Si/sub 1-x/Ge/sub x/ source structure

The bandgap engineering method using a SiGe source structure is presented as a means to suppress the floating-body effect in SOI MOSFET's. Experiments using Ge implantation are carried out to form a narrow-bandgapped SiGe layer in the source region. It has been confirmed that Ge-implanted SIMOX exhibited a 0.1 eV bandgap narrowing with a relatively low Ge-dosage of 10/sup 16/ cm/sup -2/. The fabricated N-type SOI-MOSFET's exhibited suppressed parasitic bipolar effects, such as improvement of the drain breakdown voltage or latch voltage, and suppression of abnormal subthreshold slope. Advantages over other conventional methods are also discussed, indicating that the bandgap engineering provides a practical method to suppress the floating-body effect.