Oxide Trap Research Articles

Effectiveness of Repairing Hot Carrier Degradation in Si p-FinFETs Using Gate Induced Drain Leakage

In this study, the gate induced drain leakage (GIDL) of Si p-FinFET and its recovery effect on hot carrier degradation (HCD) were experimentally studied to further its physical understanding. It’s found that HCD recovery by GIDL is more closely related to the electric field assisted discharging from oxide traps than the thermal activation. By increasing the GIDL bias, a HCD recovery ratio of up to 80% can be achieved; however, combining GIDL with an increase in environmental temperature from 75 °C to 150 °C cannot further improve the HCD recovery ratio. As the GIDL bias increases, an extraordinary interface state generation and electron injection can be observed, which responds to the remaining HCD and over-repairs the oxide trap related to the HCD. Furthermore, the effectiveness of the recovery effect of GIDL on long-term HCD was verified by comparison with HCD/GIDL and HCD/relaxation cycling experiments.

Theory of slow traps and random telegraph signals in ultra-small planar MOSFETs

It is shown that ultra-small MOSFETs with heavily doped substrates contain a significant concentration of slow traps in their space-charge regions. Such a trap arises due to random doping fluctuations and is created if a few shallow impurities form a small-scale cluster, resulting in a high binding energy of the ground state of the particle on this multiply charged “nucleus.” Inside the space-charge region, this “nucleus” is surrounded by a high potential barrier, which turns it into a slow trap with capture and emission times not too different from each other. Since a multiply charged trap scatters free carriers much more than a singly charged trap, it generates an easily observable random telegraph signal (RTS) when it captures or emits a free carrier. Such traps, located near the silicon–dielectric interface, generate high-amplitude RTSs that interfere with the normal operation of ultra-small MOSFETs. The probability of their formation depends very sharply on the doping profile near the interface. Therefore, if it can be proven that the slow traps generating the observed RTSs are in silicon, this will provide a clue to reducing this probability. This paper develops a theory describing why a multiply charged silicon slow trap can generate a high-amplitude random telegraph signal, how to reliably distinguish whether the observed RTS is generated by a silicon or oxide trap, and what experimental data are required for this. An analysis of the relevant published data for the RTSs observed in such a MOSFET shows that they are generated by slow traps located in silicon rather than in oxide. The developed theory is in qualitative and reasonable quantitative agreement with the analyzed data.

Investigation on boron diffusion effects in buried oxide of Si nanocrystals (Si NCs) embedded Silicon-on-Insulator

Si nanocrystals (Si NCs) embedded in an oxide matrix can introduce additional defects and stress, which enhances the dopant diffusion and trapping in buried oxide (BOX) layer that can be detrimental for device applications. In this paper, we have investigated the boron gettering effect of Si NCs in Silicon-on-Insulator (SOI) using Secondary Ion Mass Spectrometry (SIMS), Transmission Electron Microscopy (TEM). And image identification technique is used to analysis the Si NCs concentration in BOX. By analyzing the decline of threshold voltage and vanishing of kink effect of nMOSFET with different Si NCs concentration, it is found that the variation of boron concentration is induced by Si NCs. The higher annealing temperature and boron concentration in top Si can accelerate the boron diffusion velocity. The boron concentration rises almost tenfold in BOX layer when Si implantation dose increases from 5 × 1015 cm−2 to 5 × 1016 cm−2. The results indicate that the boron gettering effect is caused by Si NCs and highly related to the Si NCs induced defects and stress. This paper may offer a guidance for compensating the boron loss in SOI MOSFET fabricating process.

Working principle and characteristic analysis of SiC MOSFET

Power semiconductor devices are frequently used in the electronic and power industries. As the third-generation broadband gap power semiconductor devices, silicon carbide devices have attracted extensive attention. This paper introduces the internal and external structure of SiC MOSFET in detail and analyzes the basic working principle of SiC MOSFET and the electrical characteristics of each stage in the conductive process. By analyzing the theoretical calculation method of threshold voltage under body effect and the relationship diagram drawn by specific experimental test results, it is proved that the increase of body effect will lead to the decrease of the threshold voltage. Two main reasons for BTI characteristics are explained: the energy band shift of the SiC/SiO2 interface is small, and there are many charge traps at SiC/SiO2 interface. Finally, the theoretical calculation method of threshold voltage and the influence principle of threshold voltage drift caused by SiC/SiO2 interface charge: interface trap Qit, oxide trap Qot, movable ion Qm and fixed charge Qf are analyzed. The research on the basic principle and important characteristics of SiC MOSFET in this paper have important reference significance for improving the reliability of SiC MOSFET devices.

Assessment of Negative Bias Temperature Instability Due to Interface and Oxide Trapped Charges in Gate-All-Around TFET Devices

The effects of negative bias temperature instability (NBTI) on emerging tunnel FET (TFET) devices are setting of important reliability concern for analog/digital circuit design. In this work, NBTI effects in gate-all-around tunnel FET (GAA TFET) devices have been thoroughly analyzed and the unstressed p-type GAA TFET transfer characteristics are calibrated with the experimentally published data to tune the models used for the numerical analysis. The GAA device is stressed for different time durations and for different temperatures to analyze the capture and emission probabilities of the trapped charges. The effect of oxide trapping, interface trapping, and trapping of charges at several regions in the channel are analyzed individually, as well as collectively. The sub-threshold voltage of the TFET device is also investigated and it has been found that the change in the sub-threshold slope is not at all degraded by NBTI stress.

The Effect of Phycocyanin on the Microbial, Antioxidant, and Nutritional Properties of Iranian Cheese

The prevailing conditions for the production, storage, and sale of traditional cheese seem to increase the probability of microbial contamination. <i>Escherichia coli</i> and <i>Staphylococcus aureus</i> are among the bacteria that may cause major complications such as diarrhea, hemolytic uremic syndrome (HUS), food poisoning, and gastrointestinal infections in cheese consumers. The use of food coloring to enhance the microbial load of food products, as an innovative and cost-effective biological control, is one of the most efficient methods in managing the production, storage, and quality of food. Extracted naturally from <i>Spirulina</i> sp., phycocyanin is widely used in various pharmaceutical, food, cosmetic and health industries. This is the first attempt to investigate the possible effect of adding phycocyanin pigment into traditional cheese, in order to improve-the nutritional value, quality and shelf life of traditional cheese. This study collected five different types of traditional cheese from different localities in Iran. The researcher immersed the samples in concentrations of 1%, 1.5% and 2% phycocyanin pigment. After identifying the existing bacteria, the possible effect of the pigment on the total number of bacteria, as well as the number of<i> E. coli</i> and <i>S. aureus</i>, were evaluated within 15 days. The study used Ferric ion reducing antioxidant power (FRAP), 2,2-diphenyl-1-picrylhydrazyl (DPPH), and nitric oxide trapping with the sensory testing in order to determine the amount of protein, fat, ash, moisture, and antioxidant properties. Statistical analyses showed that, compared to the control group, the concentration of phycocyanin rose when the number of bacteria decreased and antioxidant activity increased in all types of cheese. The results revealed a significant increase in the amount of protein (93%), fat (80%), moisture (100%), and ash (67%). In addition, the highest consumer satisfaction was observed on day 1 and days 7 and 15; cheese with a concentrations of 1.5% and 2% pigments were preferred.

Surface band bending caused by native oxides on solution-processed twinned InSb nanowires with p-type conductivity.

Indium antimonide nanowires (InSb NWs) are attractive building-block candidates for bottom-up construction of high-efficiency electronics and optoelectronics due to their narrow direct band gap, fast room temperature carrier mobilities and small exciton binding energy. However, InSb NWs synthesized by the vapor-liquid-solution (VLS) mechanism generally suffer from an increased carrier and phonon scattering rate, which is thought to be caused by randomly distributed crystal defects along the NW growth direction. In this study, by utilizing the recently developed low-temperature, solution-processed technique, these crystal defects were successfully suppressed by periodically distributed twin planes to form twinned InSb nanowires. Importantly, measurements of the electrical transport properties of field effect transistors (FETs) reveal that the InSb NWs exhibit a hole-dominated conductivity with room temperature mobilities of up to 50.71 cm2 V-1 s-1, which is distinctly contrary to the intrinsic n-type InSb NWs. This observation of n-p switching behavior is probably attributed to the surface band bending effect with regard to the Fermi energy level, which is caused by surface oxide trap states arising from the native-oxide layer at the surface of the InSb NWs. All these results illustrate that the as-prepared colloidal InSb NWs can potentially be used as p-type materials for integration with next-generation nanoscale electronics and optoelectronics via surface engineering.

Investigation of heavy ion irradiation effects on a charge trapping memory capacitor by C–V measurement

Heavy ion irradiation effects on charge trapping memory (CTM) capacitors with TiN/Al2O3/HfO2/Al2O3/HfO2/SiO2/p-Si structure have been investigated. The ion-induced interface charges and oxide trap charges were calculated and analyzed by capacitance–voltage (C–V) characteristics. The C–V curves shift towards the negative direction after swift heavy ion irradiation, due to the net positive charges accumulating in the trapping layer. The memory window decreases with the increase of ion fluence at high voltage, which results from heavy ion-induced structural damage in the blocking layer. The mechanism of heavy ion irradiation effects on CTM capacitors is discussed in detail with energy band diagrams. The results may help to better understand the physical mechanism of heavy ion-induced degradation of CTM capacitors.

Sustainable and Selective Modern Methods of Noble Metal Recycling.

Noble metals exhibit broad arrange of applications in industry and several aspects of human life which are becoming more and more prevalent in modern times. Due to their limited sources and constantly and consistently expanding demand, recycling of secondary and waste materials must accompany the traditional mineral extractions. This Minireview covers the most recent solvometallurgical developments in regeneration of Pd, Pt, Rh, Ru, Ir, Os, Ag and Au with emphasis on sustainability and selectivity. Processing-by selective oxidative dissolution, reductive precipitation, solvent extraction, co-precipitation, membrane transfer and trapping to solid media-of eligible multi-metal substrates for recycling from waste printed circuit boards to end-of-life automotive catalysts are discussed. Outlook for possible future direction for noble metal recycling is proposed with emphasis on sustainable approaches.

Sustainable and Selective Modern Methods of Noble Metal Recycling

AbstractNoble metals exhibit broad arrange of applications in industry and several aspects of human life which are becoming more and more prevalent in modern times. Due to their limited sources and constantly and consistently expanding demand, recycling of secondary and waste materials must accompany the traditional mineral extractions. This Minireview covers the most recent solvometallurgical developments in regeneration of Pd, Pt, Rh, Ru, Ir, Os, Ag and Au with emphasis on sustainability and selectivity. Processing—by selective oxidative dissolution, reductive precipitation, solvent extraction, co‐precipitation, membrane transfer and trapping to solid media—of eligible multi‐metal substrates for recycling from waste printed circuit boards to end‐of‐life automotive catalysts are discussed. Outlook for possible future direction for noble metal recycling is proposed with emphasis on sustainable approaches.

Laser Irradiation Effect on the p-GaSe/n-HfS2 PN-Heterojunction for High-Performance Phototransistors.

Two-dimensional (2D)-based PN-heterojunction revealed a promising future of atomically thin optoelectronics with diverse functionalities in different environments. Herein, we reported a p-GaSe/n-HfS2 van der Waals (vdW) heterostructure for high-performance photodetectors and investigated the laser irradiation effect on the fabricated device. The fabricated 2D vdW heterostructure revealed a high photoresponsivity of 1 × 104 A W-1 with a photocurrent value of 377 nA due to unique type-II band alignment and enhanced surface potential under light illumination, which is further confirmed by density functional theory (DFT) calculations. Before laser irradiation, the device showed high field-effect mobility (μEF) of 26.37 cm2 V-1 s-1, ON/OFF ratio of ∼105, and threshold voltage swing (SS) of ∼463 mV dec-1. With the exposure of 690 mW cm-2 laser power density, μEF reached 204 cm2 V-1 s-1, although ∼2 V ΔVth shifts are observed along with the SS decreased to 175 mV dec-1. Interestingly, the reduced SS shows better channel control of the fabricated device with laser power. Similarly, the ON/OFF ratio decreased to ∼1.29 × 103. The results indicate that the creation of oxide trap charges at the interface of SiO2 and PN-heterojunction layers was observed with voltage biasing and high laser power density. The degradation of electrical parameters is attributed to fewer interface trap charges per surface area of the device rather than direct damage in PN-heterojunction layers. Considering the excellent 2D electronic properties, these materials are better candidates for future high-radiation environments.

Study on Total Ionizing Dose Effect of Silicon Carbide Metal Oxide Semiconductor Field-Effect Transistors at High and Low Dose Rates

The total ionizing dose (TID) radiation effect of silicon carbide metal oxide semiconductor field-effect transistors (SiC MOSFETs) was investigated at different dose rates. The influence of irradiation dose rate on the transfer characteristic curves of the devices was investigated. And the threshold voltage, oxide trap charge, interface state, and peak transconductance et al. were further extracted based on the transfer curve. The results show that the degradation degree of irradiated devices varies at different dose rates due to the different factors. The degradation of the device at high dose rate is due to the radiation-induced oxide trap charge in the gate oxide layer, while the reason of the degradation at low dose rate is the radiation-induced oxide trap charges and interface state simultaneously, which have opposite effects on the devices, and the degradation degree depends on the competition between the two.

Synapse and Tunable Leaky-Integrate Neuron Functions Enabled by Oxide Trapping Dynamics in a Single Logic Transistor

We show that a high-k gated n-MOSFET can embody both the memory plasticity of a synapse and leaky-integration of a neuron, by virtue of the rich temporal dynamics of charge capture/emission by gate-oxide defects. In addition, a tunable leaky-integrate function is demonstrated. The lower limit of energy per input spike is on the order of fJ, which provides room for low-power trigger circuit design and scalability. This work points to the prospect of a gate-engineered logic transistor serving as the universal building block of hardware spiking neural networks, thereby accelerating the realization of compact, energy efficient neuromorphic computers given the relative maturity of the transistor technology.

Linking Room- and Low-Temperature Electrical Performance of MOS Gate Stacks for Cryogenic Applications

Based on MOSFETs with four different gate stacks, we extract the oxide trap density and transconductance from the low frequency noise and DC transfer characteristics at room temperature, respectively. With the same gate stacks, Hall mobility as a function of carrier density is and the critical density is extracted at low temperatures. These physical quantities are analyzed and correlated explicitly, offering a method to qualitatively compare the quality of the four gate stacks for cryogenic MOS devices, and providing further insight into the material physics at cryogenic temperatures.

Characterization of deep traps in the near-interface oxide of widegap metal–oxide–semiconductor interfaces revealed by light irradiation and temperature change

To evaluate oxide trap state density in the near-interface region of silicon carbide metal–oxide-semiconductor (SiC MOS) stacks, photo-assisted capacitance–voltage measurements at various temperatures were performed. The difference between the deep trap profiles at SiC MOS interfaces treated with two kinds of post-oxidation-annealing was revealed, which cannot be detected by conventional evaluation methods of interface state density. With this method, the differences in the energy profile of trap levels together with their spatial distribution in the near interface region of oxide were investigated.

Designing MoS2 channel properties for analog memory in neuromorphic applications

In this paper, we introduce analog nonvolatile random access memory cells for neuromorphic computing. The analog memory cell MoS2 channel is designed based on the simulation model including Fowler–Nordheim tunneling through a charge-trapping stack, trapping process, and transfer characteristics to describe a full write/read circle. 2D channel materials provide scaling to higher densities as well as preeminent modulation of the conductance by the accumulated space charge from the oxide trapping layer. In this paper, the main parameters affecting the distribution of memory states and their total number are considered. The dependence of memory state distribution on channel doping concentration and the number of layers is given. In addition, how the nonlinearity of memory state distribution can be overcome by variation of operating conditions and by applying pulse width modulation to the bottom gate voltage is also shown.

Effect of high-radiation-dose-induced structural modifications of HfSiO4/n-Si on electrical characteristics

High-k/n-Si structures were formed with HfSiO4 films annealed at the temperature range of RT (room temperature)-900 °C and radiation-induced structural modifications were determined by XRD (X-ray diffraction) and XPS (X-ray photoelectron spectroscopy) techniques in the study. The effect of oxygen-deficient bond contents on the electrical characteristics of HfSiO4 pMOS (n type Metal Oxide Semiconductor) capacitors whose radiation response was investigated in the 0–50 kGy dose range was investigated. While no XRD peak was observed before and after irradiation at RT and 500 °C-HfSiO4/n-Si, crystallization started with irradiation at 900 °C. The dielectric constant of the film was found in the range of 16–23. It was determined that Hf–Hf oxygen-deficient bonds act as negative charge trapping centers, while Hf–Si and Si–Si oxygen-defective bonds act as positive charge trapping centers. The direction of the C–V (Capacitance-Voltage) curve changed continuously with increasing radiation dose. The change in the interface trap charge density was found to be higher than the change in the oxide trap charge density for all doses in RT-HfSiO4 pMOS capacitor and for 1 kGy at 500 °C-HfSiO4 pMOS capacitor. Oxygen defective bond content and Hf-O-Si/Si–O–Si ratios were sufficient to establish a link between structural analyses and electrical characteristics at some doses. In some cases, the frequency-dependent charges had a more dominant effect on the radiation response of the device compared to the oxide trap charges.

Characteristics of noise degradation and recovery in gamma-irradiated SOI nMOSFET with in-situ thermal annealing

This paper demonstrates a procedure for complete in-situ recovery of on-membrane CMOS devices from total ionizing dose (TID) defects induced by gamma radiation. Several annealing steps were applied using an integrated micro-heater with a maximum temperature of 365 °C. The electrical characteristics of the on-membrane nMOSFET are recorded prior and during irradiation (up to 348 krad (Si)), as well as after each step of the in-situ thermal annealing. High-resolution current sampling measurements reveal the presence of oxide defects after irradiation, with a clear dominant single-trap signature in the random telegraph noise (RTN) traces. Drain current over time measurements are used for the trap identification and further for the defects' parameters extraction. The power spectral density (PSD) curves confirm a clear dominance of the RTN behavior in the low-frequency noise. A radiation-induced oxide trap is detected at 5.4 nm from the Si-SiO2 interface, with an energy of 0.086 eV from the Fermi level in the bandgap. After annealing, the RTN behavior vanishes with a further important reduction of flicker noise. Low-frequency noise measurements of the transistor confirmed the neutralization of oxide defects after annealing. The electro-thermal annealing of the nMOSFET allows a total recovery of its original characteristics after being severely degraded by radiation-induced defects.

Simulation of low frequency noise in buried-channel MOSFET by a Green’s function-based numerical trap level model

The depletion mode Buried Chanel (BC) MOSFETs are known for their reduced Low Frequency Noise (LFN) as compared with normal Surface Channel (SC) MOSFETs in the application of Charge-Coupled Devices (CCDs) and CMOS imagers. To investigate the BC MOSFETs’ LFN mechanism comprehensively, we have developed a physical-based numerical device level simulator that accounts for the LFN contribution from each single individual oxide trap. During the simulation, the trapping current amplitude ΔID matrices are extracted efficiently by the potential-current based Green’s function. The trap capture and emission time constants are calculated via Shockley–Read–Hall (SRH) theory with Wentzel-Kramers-Brillouin (WKB) tunneling approximation. To valid our simulator, both BC and SC type MOSFETs are designed and fabricated in a CMOS imager compatible process for noise measurement and comparison. Quantitatively agreement has been obtained for both types of MOSFETs in terms of LFN spectra on a wide biasing range from the extracted process-based oxide traps’ geometry and energy sites. It reveals that the low noise operation of BC MOSFETs is inseparable from both the ΔID suppression effect and the traps’ activation energy.

Investigation on the Degradations of Parallel-Connected 4H-SiC MOSFETs Under Repetitive UIS Stresses

Parallel devices in nonuniform conditions can easily lead to reduced overall reliability or even failure due to uneven energy distribution. Especially under long-term avalanche stresses, the degradation of the device may have a great impact on the electrical parameters and performance. To study the degradation tendency and aging mechanism of parallel-connected silicon carbide (SiC) MOSFET, the repetitive unclamped inductive switching (UIS) experiments are carried out in this article. Technology computer-aided design (TCAD) simulations are utilized to simulate the temperature change and current distribution of the chip during an avalanche. The results showed that for planar and trench devices, the electrical parameters drifts are different during repetitive avalanches. The degradation rates are unequal for parallel devices with different case temperatures. Two degradation mechanisms, including hot holes injection and trapping in the gate oxide and metal aging, are found to dominate in the repetitive avalanche process. The findings are helpful for better understanding of degradations for parallel repetitive avalanches in device applications.