Output Swing Research Articles

A Modified NMOS Inverter With Rail-To-Rail Output Swing and Its Application in the Gate Driver Integrated by Metal Oxide TFTs

A modified NMOS inverter employing output feedback theme has been proposed in this paper. The feedback structure can guarantee high voltage output at a wider range of low voltage input. The proposed inverter and the conventional pseudo-CMOS inverter are both fabricated by top gate coplanar In-Zn-O thin film transistors (IZO TFTs) for comparing. The experimental results show that the proposed inverter possesses better static performance exhibiting noise margin NM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> /NM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</sub> , output swing V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OL</sub> -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OH</sub> , switching threshold V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</sub> of 3.95/5.82 V, 0.05-9.97 V, 4.05 V, respectively. In addition, the proposed inverter is also applied in the gate driver integrated by IZO TFTs to further verify its function. Benefited from good static characteristic of the proposed inverter, the output module is well controlled to produce a good output waveform. It is measured that the output waveform of the 120 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> -stage has almost no distortion compared with that of the 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> -stage at 25 kHz.

An Energy-Efficient 2 × V BAT-Swing Switched-Mode Audio Amplifier With Fully Differential Single-Inductor Linear Buck-Boost Power Topology

This letter presents a fully differential single-inductor linear buck-boost power topology-based switched-mode audio amplifier. The proposed buck-boost amplifier with single-step class-D conversion can deliver higher power to a speaker by output swing from 0 to $2\boldsymbol {\times }$ battery voltage ( $V_{\mathrm{ BAT}}$ ) while improving the efficiency by up to 10% compared to the typical two-step conversion, which uses a separate boost converter. Inductor-freewheeling with a fixed de-energizing phase linearizes the control-to-voltage conversion even in the buck-boost topology. The chip fabricated in 0.18- $\boldsymbol {\mu }\text{m}$ CMOS achieves 0.006% THD+N and 87% efficiency at a maximum output power of 5.5 W with an 8- $\Omega $ speaker load.

Simulation of Steady‐State Temperature Rise of Electric Heating Field of Wireless Sensor Circuit Fault Current Trigger

This article analyzes the structure of the wireless sensor circuit, considering the balance of power consumption, integration, area, noise, etc., and adopts a radio frequency wireless sensor circuit with a low‐IF structure. Through the analysis and comparison of traditional analog current trigger and digital current trigger structure, the feed‐forward current trigger structure is selected, which is composed of received signal strength indicator (RSSI) and variable gain amplifier (VGA), which achieves low power consumption, fast stabilization time, and wide dynamic range design. The received signal strength indicator adopts the form of approximate logarithmic amplifier, five‐stage double feedback loop structure, and realizes lower power consumption. In order to prevent the load current trigger from entering the speed saturation zone, a gain unit structure in which the superimposed current trigger is connected to the NMOS tube as the load is proposed. The test results show that the circuit has a good power consumption performance (1 mW) and at the same time 56.8 dB/m sensitivity. In this paper, through the analysis of the current trigger system and the analysis and comparison of the existing variable gain amplifiers, the variable gain amplifier structure composed of the folded wireless sensing unit and the index control unit is adopted. In order to reduce the power consumption of the circuit and increase the output swing, a structure in which the two‐stage folding wireless sensor unit shares the controlled voltage‐to‐current part of the circuit is proposed. Aiming at the design requirements of the system, this article discussed in detail the architecture of the entire temperature measurement node and the design parameters of the chip and completed the overall architecture design of the chip. The simulation results of the steady‐state temperature rise of the electric heating field show that the circuit has achieved an input dynamic adjustment range of more than 60 dB, the maximum power consumption is 1 mW, and the linearity error is less than 0.5 dB. The designed automatic gain control circuit is implemented in SMIC 0.18 cape CMOS process. The simulation results of the steady‐state temperature rise of the electric heating field show that the circuit has a 56 dB input dynamic adjustment range within a linear error of 1.25 dB, and the time constant is 7.55 ms, and power consumption is 2.84 mW. Through the steady‐state temperature rise simulation and test results of the electric heating field, the correctness of the design is verified and it meets the system requirements.

Design Techniques for High-Speed Wireline Transmitters

Wireline transmitters operating at tens of gigabits per second pose challenging design issues ranging from limited bandwidths to severe sensitivity to jitter. This paper presents a number of analog and digital circuit techniques that allow data rates as high as 80 Gb/s in 45-nm CMOS technology. A PAM4 prototype delivers an output swing of 630 mV $_{pp}$ with a clock jitter of 205 fs $_{rms}$ while drawing 44 mW.

Influence of Bifurcation Pipe Position on Hydraulic Turbulence for Pumped Storage Power Station

There must be hydraulic turbulence transient in the pumped storage power station with one pipe corresponding to several units. This paper established a simulation model by using the method of characteristics for a pumped storage power station to analyse how the change of upstream and downstream bifurcation pipe position and different arrangements of downstream surge tank affect the hydraulic turbulence. The results indicate that unit output’s amplitude of power mode is smaller than that of frequency mode. And the upstream and downstream bifurcated pipes far away from the units can reduce the hydraulic turbulence of normal operating unit while the upstream without bifurcation pipe is better than the downstream without bifurcation pipe to control the output swing. Sharing the downstream surge tank can effectively reduce the maximum relative over output of the unit, while the surge tank placed in the downstream branch pipe will worsen turbulence process.

Super-Gain-Boosted AB-AB Fully Differential Miller Op-Amp With 156dB Open-Loop Gain and 174MV/V MHZ pF/μW Figure of Merit in 130nm CMOS Technology

A fully differential Miller op-amp with a composite input stage using resistive local common-mode feedback and regulated cascode transistors is presented here. High gain pseudo-differential auxiliary amplifiers are used to implement the regulated cascode transistors in order to boost the output impedance of the composite input stage and the open-loop gain of the op-amp. Both input and output stages operate in class AB mode. The proposed op-amp has been simulated in a 130nm commercial CMOS process technology. It operates from a 1.2V supply and has a close to rail-to-rail differential output swing. It has 156dB DC open-loop gain and 63MHz gain-bandwidth product with a 30pF capacitive load. The op-amp has a DC open-loop gain figure of merit $FOM_{AOLDC}$ of 174 (MV/V) MHz pF/ $\mu \text{W}$ and large-signal figure of merit $FOM_{LS} $ of 3(V/ $\mu \text{s}$ ) pF/ $\mu \text{W}$ .

A Deep Subelectron Temporal Noise CMOS Image Sensor With Adjustable Sinc-Type Filter to Achieve Photon-Counting Capability

This letter introduces a Gm-cell-based CMOS image sensor (CIS) achieving deep subelectron noise performance. The CIS presents a new compensation block and low-noise current source to improve the performance of the Gm pixel. Furthermore, an optional first-order IIR filter is implemented to improve the output swing. The conversion gain, full well capacity, and dynamic range of the CIS can be easily adjusted by the charging time and the filter mode for different applications. The prototype chip is fabricated in a standard 180 nm CIS process and has a deep subelectron read noise of 0.31e-rms at minimum (of the noise distribution) and 0.42e-rms at peak (of the noise distribution). A smooth and clear photon-counting histogram is observed.

Analog Operation Temperature Dependence of nMOS Junctionless Transistors Focusing on Harmonic Distortion

This paper performs a comparative study of the analog performance of Junctionless Nanowire Transistors (JNTs) and classical Trigate inversion mode (IM) devices focusing on the harmonic distortion. The study has been carried out in the temperature range of 223 K up to 473 K. The non-linearity or harmonic distortion (HD) has been evaluated in terms of the total and the third order distortions (THD and HD3, respectively) at a fixed input bias and at a targeted output swing. Several parameters important for the HD evaluation have also been observed such as the transconductance to the drain current ratio (gm/IDS), the Early voltage (VEA) and the intrinsic voltage gain (AV). Trigate devices showed maximum AV around room temperature whereas in JNTs the intrinsic voltage gain increases with the temperature. Due to the different AV characteristics, Junctionless transistors present improved HD at higher temperatures whereas inversion mode Trigate devices show better HD properties at room temperature.When both devices are compared, Junctionless transistors present better THD and HD3 with respect to the IM Trigate devices.

A 0.59-mW 78.7-dB SNDR 2-MHz Bandwidth Active-RC Delta-Sigma Modulator With Relaxed and Reduced Amplifiers

This article presents a circuit technique to improve the power efficiency of the well-established active-RC continuous-time (CT) Delta-Sigma modulator (DSM). The technique is to add a large capacitor at the virtual ground node of the first amplifier in an active-RC DSM. Without attenuating the in-band signal, this capacitor smooths out the fast transitions in the feedback and suppresses most of the quantization noise before processing by the first amplifier. The transconductance and output swing requirements of the crucial first amplifier can therefore be significantly relaxed. In addition, the technique converts an undesired parasitic pole into a desired one of the loop filter, reducing an amplifier and eliminating the problems associated with the parasitic pole. Last, the large capacitor at the virtual ground node opens a way to reduce the flicker noise because it allows the first amplifier to use large-sized input transistors without performance penalties. To verify the technique, a 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> order 1-bit active-RC DSM is designed and fabricated in 180-nm CMOS technology. Clocked at 320 MHz, it achieves a measured signal-to-noise-plus-distortion ratio of 78.7 dB over a 2 MHz bandwidth and a spurious-free dynamic range of 88.4 dB while consuming 0.59 mW, of which the first amplifier takes only 13.5%. The recorded Warden's and Schreier's figure of merits are 20.1 fJ/conv-step and 174 dB respectively. The proposed simple circuit technique makes this otherwise ordinary active-RC modulator one of the most power-efficient CT DSMs.

Design of Transfer-Gated CMOS Active Pixels Deploying Conventional PN-Junction Photodiodes

This paper presents a comparative study of six active pixel sensor (APS) schemes by means of simulations and experiments. The optical sensor used was a silicon photodiode with integrated electronics in a standard 0.35 µm CMOS technology. We analyzed how the transistor characteristics, such as channel resistance and leakage current, among others, can influence the APS response. Furthermore, we demonstrated how the choice of APS model affects sensor parameters such as output swing and fill factor, among others. The results presented and the understanding of the operational cycle of the CMOS transfer-gated APS aims at guiding better choices for different applications and the better transistor type in the project.

A 25-Gb/s inductorless SiGe BiCMOS receiver for 100-Gb/s optical links

This paper presents the design and measurements of a 25-Gb/s inductorless optical receiver in a 0.25-μm SiGe BiCMOS process for 100-Gb/s (25-Gb/s × 4 lines) Ethernet. As the first stage of the proposed optical receiver, a transimpedance amplifier (TIA) employing a pseudo-differential structure with a feedback resistor incorporates DC offset cancellation (DOC) to enhance the input dynamic range. Cascaded by the improved two-stage limiting amplifiers and a 50-Ω output buffer, the receiver achieves high differential swings. For a bit-error rate (BER) of 10−12 at 25 Gb/s, the measured transimpedance gain, bandwidth, sensitivity, and output swing are 63.17 dBΩ, 20.7 GHz, −10.3 dBm, and 352.7 mV, respectively. The power consumption of the entire receiver is 111.6 mW and the core area of the die is 640 μm × 135 μm.

A 6.5-μW 10-kHz BW 80.4-dB SNDR Gm-C-Based CT ∆∑ Modulator With a Feedback-Assisted Gm Linearization for Artifact-Tolerant Neural Recording

This article presents a Gm-C-based continuous-time delta-sigma modulator (CTDSM) for artifact-tolerant neural recording interfaces. We propose the feedback-assisted Gm linearization technique, which is applied to the first Gm-C integrator by using a resistive feedback digital-to-analog converter (DAC) in parallel to the degeneration resistor of the input Gm. This enables the input Gm to process the quantization noise, thereby improving the input range and linearity of the Gm-C-based CTDSM, significantly. An energy-efficient second-order loop filter is realized by using a voltage-controlled oscillator (VCO) as the second integrator and a phase quantizer. A proportional-integral (PI) transfer function is employed at the first integrator, which minimizes the output swing while maintaining loop stability. Fabricated in a 110-nm CMOS process, the prototype CTDSM achieves a high input impedance, 300-mVpp linear input range, 80.4-dB signal-to-noise and distortion ratio (SNDR), 81-dB dynamic range (DR), and 76-dB common-mode rejection ratio (CMRR) and consumes only 6.5 μW with a signal bandwidth of 10 kHz. This corresponds to a figure of merit (FoM) of 172.3 dB, which is the state of the art among the neural recording ADCs. This work is also validated through the in vivo experiment.

Efficiency‐enhanced and high‐precision of input common‐mode feedback control using OSA–CLS technique

Efficiency-enhanced and high-precision input common-mode feedback control (ICMFB) is proposed for a fully differential readout circuit of the MEMS capacitive sensor. This ICMFB improves the efficiency and performance of input common-mode voltage control using a smaller feedback capacitor. The noise performance of the readout circuit is improved as a decrease of a feedback capacitor. The correlated level shift (CLS) technique is used to improve the output swing of the amplifier therefore reduce the value of a feedback capacitor. Also, the oversampling successive approximation (OSA) technique is used to improve the accuracy of input common-mode voltage control using a low-gain op-amp. Simulation results show that the input common-mode voltage error decreases to 0.01% when the value of the feedback capacitor is the same as the MEMS sensor. Also, the noise power spectral density of the readout circuit increases by 10 dB.

High-Speed Ring Oscillator Using Skewed Delay Scheme Integrated by Metal-Oxide TFTs

This article presents a novel design of high-speed ring oscillator (RO) in n-type-only indium-zinc-oxide (IZO) thin-film transistor (TFT) technology. The proposed ROs combine the advantage of the skewed delay (SD) scheme and the bootstrap inverter to achieve a higher oscillation frequency. The design of improved output buffers with stronger driving capability is also included. For comparison, the proposed seven-stage SD ROs and the conventional bootstrap RO are fabricated on the same glass. It is measured that the oscillation frequencies of the SD ROs with -t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pd</sub> and 0 SD are improved by more than 45% and 25% within the supply voltage ranges from 6 V up to 20 V. In addition, the measured output swings of the proposed boost buffers are improved by more than 50% with input frequencies higher than megahertz.

A PVT aware differential delay circuit and its performance variation due to power supply noise

Delay circuits are one of the key components in time domain blocks such as pulse width modulator. This work describes the working of a differential delay circuit under process, voltage and temperature. The proposed design is also coupled to a typical power delivery network (PDN) and a central processing unit (CPU) core ramping current from 0 A to 10–40A in 10 ns Simulated in a 90-nm CMOS technology and power supply voltage (Vdd) of 1.1 V, the post-layout delay was noted to be 227 ps During this time, differential signals at the input are switching at 1GHz while the rise, fall times are about 0.1ns The power thus dissipated corresponds to 235 μW. But, delay changes by about 0.4–0.9 ps at every process corner while temperature increases by 1OC. The corresponding variation for 1mV drop in power supply voltage is 0.1–0.4ps In addition to that, a change in temperature enables the average power to fluctuate between 192.8 and 264μW, whereas, 0.6μW for 1mV drop in power supply voltage. The study of 500 runs Monte-Carlo analysis for a NN process indicates an almost identical behavior with the no skew data in post-layout. The rms jitter is within 0.01–0.3ps while the delay per mV change in power supply is 0.21 ps/mV. But a sudden current drawn by the CPU causes the voltage VP close to the die to oscillate. This enables the delay to vary than those obtained with zero power supply noise. The sudden current also introduces jitter in the output swing. The jitter so induced varies linearly with the AC first droop.

Low Voltage Delay Element with Dynamic Biasing Technique for Fully Integrated Cold-Start in Battery-Assistance DC Energy Harvesting Systems

This paper proposes an ultra-low voltage delay element for battery-assistance DC energy harvesting systems. By inserting a low voltage level shifter (VLS), a wider voltage range is obtained to bias the body of the delay element. Thus, both the voltage transfer curve (VTC) and the DC gain of the delay element are enhanced. Due to the introduction of the VLS, the cold start-up ring oscillator constituted by the proposed delay element can achieve oscillation under an extremely low input voltage. The fully integrated cold start-up ring oscillator with 21 stages of the proposed element is implemented in a standard 180 nm complementary metal oxide semiconductor (CMOS) process. The post-layout experimental results indicate that the cold start-up ring oscillator can retain oscillation when the power supply voltage (VDD) is 24 mV under a typical corner at room temperature. The output voltage swing of the cold start-up ring oscillator based on the proposed delay element is improved by more than 55% under VDD = 40 mV compared with a stacked inverter-based cold start-up ring oscillator. Monte Carlo (MC) simulation from 100 samples shows the enhanced output swing with the proposed delay element under process variation.

Implementation of an Ultra Low Power Process-Insensitive Two Stage Complementary Metal Oxide Semiconductor Operational Amplifier with Enhanced Direct Current Gain at 45 nm Technology Node

This paper presents an ultra low power process-insensitive two stage CMOS OP-AMP employing bulk-biasing technique realised in a standard 45 nm CMOS technology. Bulk-Biasing technique has been employed to augment the DC gain of two stage CMOS OP-AMP without having any impact on its power dissipation and output swing. In this work, high gain-bandwidth product (GBW) with appropriate phase margin is achieved through pseudo-cascode compensation approach which overcomes the drawbacks of Miller compensation technique also. Furthermore, the effect of width scaling on performance metrics of proposed OP-AMP has been analysed. The designed OP-AMP exhibits enhanced DC gain of 94.2 dB, gain-bandwidth product (GBW) of 460 MHz and adequate phase margin of 80°; with fast settling response. Also, the proposed OP-AMP has power dissipation of 27 μW and leakage current of 6.4 pA only. The design and optimisation of proposed OP-AMP is carried out at a power supply of 0.7 V under room temperature in Cadence Virtuoso tool.

Development of a high-performance readout circuit for photoelectric detectors

A high-performance readout circuit for photoelectric detectors is developed in this paper to achieve high-speed low-noise image detection. Here, the W/L ratio of the first-stage P-type following transistor is reduced to decrease the parasitic capacitance of buses, and the bias voltage of the P-type following load transistor is minimized to increase the driving current. These changes increase the sampling frequency of the read-out circuit from its original 2 MHz to 6 MHz, thereby effectively improving the readout frequency of the long-line visible light CMOS detector. Four-sampling is used to achieve true correlated double-sampling and reduce the equivalent input noise of the device, thus, overcoming the original circuit’s non-true correlation cancellation. Testing revealed that the number of equivalent input noise electrons of the CMOS detector decreased from 100e to 50e (rms) when the integral time is 200 µs and the photosensitive area is 20 × 18 μm2. The device could work steadily at a sampling rate of 6 MHz, and its linearity and output swing exceed 99% and 2 V, respectively. Moreover, the sensitivity of the detector could meet the requirements of the system. The development of the proposed CMOS detector lays an important theoretical foundation and provides practical value for future research on ultra-high speed and high-definition image detection technologies.

An improved MASH sigma-delta modulator with all-anolog interstage and input-feedforward architecture

ABSTRACT This paper puts forward an improved multi-stage noise-shaping (MASH) sigma-delta modulator. Derived from a fourth-order two-stage MASH architecture with adder-less architecture of cascade of integrators with feedforward (CIFF), the proposed modulator improves the method of extracting quantization noise of the first stage to form an all-analog interstage, and two input-feedforward paths are added to the second stage to reduce the output swing of the integrator. Analyses and measurements indicate that the proposed architecture has lower in-band quantization noise power, higher signal-to-quantization noise ratio (SQNR), and lower power consumption and complexity as well. When operating from a 1.2 V supply, the modulator achieves 107.56 dB peak SQNR, 71.8 dB peak Signalnoise and distortion ratio while consuming 26 mW, with an OSR of 8 at a 160 MHz sampling frequency.

A Dual-Polarization Silicon-Photonic Coherent Transmitter Supporting 552 Gb/s/wavelength

Coherent optical links improve spectral efficiency over their intensity-modulation direct-detect (IM-DD) counterparts using advanced modulation schemes such as quadrature phase shift keying (QPSK) and quadrature amplitude modulation (QAM), and by utilizing dual polarization (DP) of light. This increase in spectral efficiency also leads to stringent requirements for the link components. The transmitter (TX) must simultaneously achieve high bandwidth (BW), linearity, output swing, and reliability. In this article, we present a silicon-photonic Mach–Zehnder modulator-based optical TX on an Silicon-on-Insulator (SOI) process, and linear, high-swing SiGe drivers on 130-nm BiCMOS process. The output stage of the driver uses a voltage breakdown enhancement technique to ensure the reliability of the TX. A resistor-based capacitor splitting technique is introduced, and aided by other methods such as zero-peaking and degeneration, the targeted gain, BW, swing, and linearity for the driver are realized. The driver achieves a differential swing of 6 V peak-to-peak, a total harmonic distortion (THD) of 3.6%, and more than 40 GHz of electrical BW. Co-designed and co-packaged with the silicon-photonic modulators, the TX achieves 272 Gb/s/wavelength with DP-16 QAM at 6-V peak-to-peak driver swing and exceeds 0.5 Tb/s/wavelength data rates with DP-16 QAM at 2.4-V peak-to-peak driver swing. The low-cost, compact, and all-Si/SiGe design matches the required optical SNR performance of LiNbO3 modulators with III–V drivers at 34 Gbaud.