Ternary Logics Based on 2D Ferroelectric-Incorporated 2D Semiconductor Field Effect Transistors

Abstract

Ternary logic has been proven to carry an information ratio 1.58 times that of binary logic and is capable to reduce circuit interconnections and complexity of operations. However, the excessive transistor count of ternary logic gates has impeded their industry applications for decades. With the modulation of the ferroelectric negative capacitance (NC) properties on the channel potential, MOSFETs show many novel features including steep subthreshold swing and non-saturation output characteristics, based on which an ultra-compact ternary inverter can be achieved. Compared with traditional bulk materials, layered 2D materials and 2D ferroelectrics provide a clean interface and better electrostatic control and reliability. Even though ultra-low SS (∼10 mV/dec) has been experimentally demonstrated in ferroelectric-negative capacitance-incorporated 2D semiconductor (NC2D) FETs, the available models are still rare for large-scale circuit simulations. In this study, the superb electrical properties of pure 2D material stack-based NC2D FETs (layered CuInP2S6 adopted as the 2D ferroelectric layer) are investigated through device modeling based on the Landau–Khalatnikov (LK) equations in HSPICE. We managed to realize an ultra-compact ternary inverter with one NC2D-PMOS (WSe2) and one NC2D-NMOS (MoS2) in HSPICE simulations, whose transistor count is significantly reduced compared with other counterparts. We also proposed a novel input waveform scheme to solve the hysteresis problem caused by ferroelectric modulation to avoid logic confusion. Additionally, the power consumption and propagation delay of the NC2D-based ternary inverter are also investigated. This work may provide some insights into the design and applications of ferroelectric-incorporated 2D semiconductor devices.