Abstract

With the approaching end of Moore’s Law (that the number of transistors in a dense integrated circuit doubles every two years), the logic data density in modern binary digital integrated circuits can hardly be further improved due to the physical limitation. In this aspect, ternary logic (0, 1, 2) is a promising substitute to binary (0, 1) because of its higher number of logic states. In this work, we carry out a systematical study on the emerging two-dimensional (2D) materials (MoS2 and Black Phosphorus)-based ternary logic from individual ternary logic devices to large scale ternary integrated circuits. Various ternary logic devices, including the standard ternary inverter (STI), negative ternary inverter (NTI), positive ternary inverter (PTI) and especially the ternary decrement cycling inverter (DCI), have been successfully implemented using the 2D materials. Then, by taking advantage of the optimized ternary adder algorithm and the novel ternary cycling inverter, we design a novel ternary ripple-carry adder with great circuitry simplicity. Our design shows about a 50% reduction in the required number of transistors compared to the existing ternary technology. This work paves a new way for the ternary integrated circuits design, and shows potential to fulfill higher logic data density and a smaller chip area in the future.

Highlights

  • Integrated circuits (IC) are the cornerstone of modern information society and are widely used in almost all of the electronic systems

  • We perform a systematical study on the 2D-materials-based ternary logic from individual ternary logic gates to large scale integrated circuits

  • We design and fabricate various ternary logic gates with different logic functions, which show good ternary performance with simplified circuital structure compared to traditional silicon ternary and CNT ternary

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Summary

Introduction

Integrated circuits (IC) are the cornerstone of modern information society and are widely used in almost all of the electronic systems. The performance of binary logic is fundamentally limited by its low density of logic states, that is, only two logic levels (0, 1) can be transmitted over a given set of lines [1] It needs a large number of logic gates and transistors to reach the required data size. Many groups have focused their attention on the demonstration of ternary logic gates using multi-threshold CNTFETs [11,12,13,14,15] In their designs, no passive resistive components were needed, but the simplest ternary NOT gate still needed six CNTFETs, which was much more complicated than that of a classical CMOS binary NOT gate The decrement cycling inverter and the optimized ternary adder algorithm will be used to design the 19-trit ternary adder

Demonstration of Ternary Logic Gates
Demonstration of different ternary
Functional Ternary Logic Gates
Conventional Design of Ternary Adder
Our Optimized Design of Ternary
Design
Findings
Conclusions
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