A 16-Times Frequency Multiplier for 5G Synthesizer

Abstract

This article presents 16-times frequency multiplier composing of two four-times frequency multipliers (quadrupler) in cascade connection. The proposed topology is new structure of tuned-frequency multiplier (TFM) for better harmonic rejection ratio (HRR) with wide frequency range and low power consumption. For accomplishing reliable output frequency band of 16–28 GHz, the whole band is divided into 64 subsidiary frequency bands by applying 6-bits digitally controlled capacitor-bank of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> -tuned tank. The proposed quadrupler is consisted of a harmonic generator (HG) and a cascode <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> -tuned buffer. The proposed HG topology is based on double balanced mixer (DBM). Unlike typical mixer bias, the bottom differential pair devices of the proposed HG are C-class biased to generate more desired the fourth order harmonic. In addition, to reduce power consumption and frequency conversion gain variations for the whole target frequency band, negative- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$g_{m}$ </tex-math></inline-formula> differential pair is added in parallel to enhance the equivalent parasitic parallel resistance of the HG <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> -tank while keep it from oscillation. Great efforts have been contributed to minimize process variation effects by simple but relatively accurate capacitance calibration. Furthermore, each <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> -tuned tank output amplitude is regulated by a loop to maintain same output swing for the best optimization of specifications such as power consumption and HRR. The proposed 16-times multiplier is fabricated on 65-nm complementary metal–oxide–semiconductor (CMOS) process and successfully tested. Chip die size 0.7 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> excluding input/output (I/O) pads and average power consumption is only 6 mW for 16–28 GHz frequency band. Also, negligible phase noise degradation is achieved.