A Low Power SAR ADC with Digital Error Correction Technique for Wearable and Implantable ECG Devices

Abstract

Aims: This study aims to propose an 8-bit differential input low-power Successi,e Approximation Register (SAR) ADC with digital error correction technique for sensing bio-potential signals in wearable and implantable devices. Background: As dynamic comparators have the advantages of full swing output, low power consumption, high speed, and high impedance at the input, they are preferably used in energy-efficient SAR ADC’s. However, since the dynamic comparator is the most frequently used block in SAR ADC, research is ongoing to reduce its μW power further. Also, as the offset voltage of the comparator affects the linearity of ADC, it must be minimized. Linearity can further be improved by calibrating the output of ADC, and extensive surveys on the calibration methods prove that the addition- only digital error correction method is efficient in terms of power. Objective: The objective of this study is to design a low-power and low-offset dynamic comparator intended for SAR ADC to achieve highly linear digital output. In addition to this, the objective is to implement a power-efficient digital error correction technique for the output of SAR ADC to overcome the non-idealities due to process variations. Method: As power consumption is proportional to the number of transistors, the proposed comparator is a design obtaining the same output as the existing dynamic comparators with reduced transistor count. The proposed comparator, along with low power full swing three-input XOR logic gate, is implemented in SAR ADC with digital error correction technique in cadence 45 nm technology files, and its performance parameters are simulated. Results: The layout of the proposed dynamic comparator occupies an area of 3 μm2. The simulation results of this comparator with a load of 1 pF show that it has a total offset of 11.2 mV, a delay of 0.9 ns, and power consumption of 24 nW. It also achieves a gain of 49.5, i.e., 33.86 dB. The 8-bit ADC, along with the digital error correction technique operating at 143-kS/s and under 0.6 V supply voltage simulated in 45nm technology, consumes only 0.12 μW of power. The DNL and INL errors obtained are +0.22/-0.2 LSB and -0.28 LSB, respectively. SNR limited by noise is 48.25 dB, SFDR is 48.64 dB, and ENOB achieved is 7.72. Conclusion: To satisfy the requirement of the wearable and implantable devices, a low-power SAR ADC with good linearity is designed using a low-power and low-offset dynamic comparator. A digital error correction technique using a low-power XOR logic gate is implemented at the SAR ADC output to minimize the non-idealities due to the process variations.