Output Return Loss Research Articles

Ultracompact isolated multilayer broadside-coupled balun with arbitrary isolation bandwidth

Abstract An isolated low-profile multilayer all-ports-matched broadside-coupled balun (BCB) with arbitrary isolation bandwidth is presented. Analytical relations are derived and provided for the isolation circuit (IC) design in terms of electrical and physical parameters. Accordingly, instructions are given on obtaining optimum bandwidth and isolation responses for the IC. Design procedure for the BCB is presented together with a case study for power amplifier application. The BCB is validated theoretically, analytically, and experimentally, and results are in good agreement. The fabricated balun has insertion loss of 0.27 dB, input and output return losses of 19 dB, isolation of 20 dB at fc, and phase and magnitude imbalance better than 2° and 0.2 dB across the Bandwidth (BW), respectively. The realized isolated balun has dimensions of 0.06λg × 0.03λg.

Design of high gain MMIC amplifier for LEO satellite communication systems

In this paper, we present a novel design of S-band monolithic microwave integrated circuit (MMIC) amplifier based on GaAs Mesfet HFET-1102 transistor used in radiofrequency (RF) and microwave communications system. Basing on Chebyshev gain response an analytical method is used to design two stages lumped microwave amplifier. The matching networks constituted by lumped elements are transformed to T inductive networks and the resulting amplifier is optimized using RF simulator software. Thelumped optimized amplifier is then transformed to distributed amplifier and implemented on Rogers TMM3 substrate, largely used in microwave circuits. The proposed MMIC distributed amplifier is stable in the frequency band (2–4 GHz) and excellent performances are obtained in terms of very high gain reaching a peak of 34.23 dB, minimum input return loss (S11) of −8.85 dB at f=2.62 GHz, minimum output return loss (S22) of −12.21 dB at f=2.05 GHz and very good output/input isolation (S12) lower than −51.99 dB. For its excellent performances, the proposed MMIC distributed amplifier, is very suitable for use in space telecommunications as in Low Earth Orbit (LEO) satellites onboard receivers where the high gain amplifier is very important to assure the success of the space missions.

Design of advanced dielectric RF windows for dual-band Gyro-TWT

In this paper, the design of different dielectric advanced ceramic materials of RF windows for dual-band K-band and Q-band Gyro-TWT has been described. The design methodology of quartz, magnesium aluminate (MgAl2O4) and sapphire dielectric windows of operating TE01 mode for K-band and Q-band Gyro-TWT has been discussed. The simulation result predicts that these windows can handle 100 kW output power and return loss −58.5 dB and insertion loss −0.02 dB. This paper presents the electrical design and thermal analysis of K-band and Q-band dual-band Gyro-TWT amplifier. In the thermal analysis, the maximum temperature has been obtained at the centre of the dielectric disc. The electro-mechanical analysis has also been carried out on the different dielectric windows to achieve stress and displacement. A new type and unique advance transparent dielectric material magnesium aluminate (MgAl2O4) disc window has been used to improve the bandwidth performance of Gyro-TWT.

A Compact GaN Power Amplifier Module for New Generation Cellular Basestations

This paper presents a compact class-AB Power Amplifier Module (PAM) designed for new generation massive Multiple Input Multiple Output (MiMo) cellular base stations. The module is designed at the center frequency of 3.5GHz targeting Long Term Evolution (LTE) and 5G New Radio (NR) bands. The module is a hybrid design that incorporates a Gallium Nitride (GaN) High Mobility-Electron Transistor (HEMT) die, discrete components-based input, and output matching networks. The entire design is realized on an 8.5 x 5.2 mm, 2-layer Rogers4003C substrate. The module is assembled on a PCB as an open-top for post-characterization tuning. The small signal and large signal measurements are in quite good agreement. The measurement results show that the amplifier is unconditionally stable, the input return loss is 12.2 dB, the output return loss is 7.7 dB, and the small signal gain is 13.4 dB. The saturated output power is 33.3 dBm with a Power Added Efficiency of 20.1%. The small signal gain drops to 11.2 dB at around 22 dBm of input power due to GaN technology’s intrinsic soft compression characteristics.

2–26.5 GHz GaN ultra‐wideband amplifier with over 2 W output power

AbstractA 2–26.5GHz broadband amplifier monolithic microwave integrated circuit (MMIC) based on the 0.15 μm GaN high electron mobility transistor process has been developed. The broadband amplifier adopts a two‐stage distributed amplifier cascade structure, which improves the gain of the broadband amplifier. Further, the capacitive coupling is used to improve the gain bandwidth product of the power amplifier. To improve the output return loss of the wideband amplifier, a tuning stub is introduced at the output of the circuit. The on‐wafer measurement results show that the amplifier has a gain greater than 18 dB, gain flatness less than ±1.4 dB, and saturated output power >35 dBm with a >13% power added efficiency in the whole band.

A broadband low‐loss SPDT RF switch using a new off‐chip compensation technology

SummaryAn off‐chip compensation technology for low‐loss and broadband characteristics of radio frequency (RF) switches is proposed based on mathematical analysis of series shunt single pole double throws switches in this letter. This compensation technology can absorb the parasitic parameters of the switch Field Effect Transistor, improving the insertion loss and return loss of the switch as well as supporting higher bandwidth. To verify the design principle, a RF switch, using the SANAN GaAs 0.15 um pseudomorphic High Electron Mobility Transistors (pHEMT) process, and an off‐chip compensation network were designed and implemented. Specifically, after using an off‐chip compensation network, the measured bandwidth of switch has been expanded from 1.1–8.8 to 0.8–11 GHz, while the input and output return loss have also improved significantly.

Harmonic Suppressed Wilkinson Power Divider Using Parallel Resonant Shunt Stub

This paper proposes a harmonic-suppressed Wilkinson power divider (HS WPD) utilizing parallel resonant shunt stubs (PRSSs). PRSSs are integrated into the conventional WPD by adding functionalities such as bandpass filtering, harmonic suppression, and physical port separation. The resonance conditions and design equations of the PRSS are theoretically derived and verified through circuit simulations. Using the PRSS, we designed an HS WPD operating at 1 GHz. The fabricated HS WPD demonstrated an insertion loss of 3.2 dB at the fundamental frequency, with a wide 3 dB bandwidth of 129%. The harmonic suppression levels at the 2nd and 3rd harmonic frequencies are measured to be 21.0 dB and 25.8 dB, respectively. The measured input return loss at the fundamental frequency was 27.9 dB, whereas the output return loss was 24.6 dB. Additionally, the HS WPD demonstrates isolation levels at the fundamental, 2nd, and 3rd harmonic frequencies, with levels of 29.2 dB, 17.8 dB, and 47.1 dB, respectively. It also exhibited broadband isolation (>8.7 dB) across the frequency range of 100 kHz to 3.35 GHz. The PRSS design allows for the physical separation of the ports without requiring additional circuitry. Compared to previously reported PDs, the proposed design offers multiple functions in a compact size, making it highly suitable for various microwave systems.

A 8–12 GHz power amplifier with high out-of-band rejection

This paper proposes an 8–12 GHz monolithic power amplifier (PA) with high out-of-band rejection. This PA adopts an impedance conversion technique to reduce the Q of the output impedance of the amplifiers for all stages, which is used to achieve broadband matching performance. In addition, the bandpass matching structures and a trap circuit are adopted to effectively suppress out-of-band signals. The proposed PA is fabricated by using a 0.5 μm GaAs pHEMT process. The measurement results show that the PA has an in-band small signal gain of 23 dB ± 0.7 dB, input and output return loss are both better than −14dB, the saturation output power is about 23dBm, the power-added efficiency (PAE) is better than 20 %, and rejection ratios are 65dBc and 51dBc at 3 GHz and 17 GHz respectively. The area is of 2.3mm × 1.1 mm.

Optimization Technology of the Microwave Diplexer Based on Spatial Mapping Algorithm

An optimization technology of the microwave diplexer is proposed in this paper. The spatial mapping algorithm has been adopted to analyze and design the microwave diplexer, and the mapping relationship between the physical circuit (accurate model) and the schematic circuit (rough model) has been established, and then the least square method has been applied to fit it. Moreover, the inverse mapping method has been applied to guide the design of the accurate model by the optimization of the rough model. To verify the presented optimization technology of the microwave diplexer, a diplexer with the center frequencies of 1.85 GHz and 2.4 GHz respectively is designed, optimized, and fabricated. The measured results show that the insertion loss is about 0.8/1.5 dB. The measured output return loss is greater than 20 dB. Moreover, the measured isolation between two channel is greater than 35 dB. The total size of the fabricated diplexer is only 0.25λg 0.2λg. The measured results are in good agreement with the simulated ones, which was able to demonstrate the feasibility and advantage of this algorithm in designing microwave diplexer circuits.

Design of 3.1-10.6 GHz UWB CMOS Power Amplifier using Cascade Topology

Power amplifier is an important component in the wireless communication system. Design of the power amplifier in UWB transceiver is challenging as the signal need to be transmitted over a wide bandwidth. Several criteria need to be fulfilled such as good linearity, good wideband matching, high efficiency and low power consumption. This paper presents the design of a power amplifier with 3.1-10.6 GHz using 0.18 μm CMOS technology for ultra-wide band application. The proposed power amplifier used three cascaded amplifier stages in order to achieve good gain and wide-band width. The results show that the proposed power amplifier design has an average gain of 7.28 dB, an input return loss less than -7.48 dB, an output return loss less than -4.782 dB, and group delay variation of ±151.9 ps is achieved over the entire band. A good input 1dB-compression point of 6.67 dBm and input third order intercept point of 0 dBm is achieved at 5 GHz.

An S-band MMIC LNA in GaAs 0.15-μm pHEMT

The study adopts a monolithic microwave integrated circuit (MMIC) low-noise amplifier (LNA) applied in S-band was designed using ADS simulation software, GaAs 0.15-um pseudomorphic high electron mobility transistor (pHEMT) process. The LNA small signal gain is greater than 30.8 dB, gain flatness is ±0.45 dB, noise coefficient is less than 1.5 dB, input and output return loss is greater than 10 dB, and the chip area is 1.2*2.4 mm2. The low noise amplifier is composed of a two-stage cascade structure. Gain flatness, gain control, and bandwidth broadening are improved by RLC negative feedback network. The minimum noise coefficient circle and maximum gain circle are narrowed by adding negative feedback to achieve better noise coefficient and gain.

A Ku-Band CMOS Balanced Driver Amplifier With Transformer-Based Notch Filter for SATCOM Phased Arrays

This brief presents a Ku-band balanced driver amplifier (BDA) for SATCOM phased arrays. To facilitate a flexible and low-loss coupler design, the non-correlation between the coupling coefficient and the output power of BDA is illustrated. The passive transformer-based notch filter is co-optimized with the inter-stage matching network. The sideband rejection is improved while maintaining high gain and linearity. The second harmonic trap technique is also applied to alleviate the amplitude-to-phase (AM-PM) distortion. Fabricated in 65-nm CMOS technology, the proposed BDA provides the maximal gain of 26 dB at 14 GHz with the highest sideband rejection of 26 dB. The input and output return losses are both better than -15 dB. It achieves a measured 1-dB compressed power (P1dB) of 19.5 dBm with the maximal power-added efficiency (PAEmax) of 27.8%. The small-signal gain and P1dB vary only 2 dB and 0.8 dBm from -55∘C to 85∘C, respectively.

A Sub-GHz CMOS SPDT Antenna Switch Employing Linearity-Enhanced Biasing Strategy for Second-Order Harmonic Reduction

A CMOS single-pole double-throw (SPDT) antenna switch employing linearity-enhanced biasing strategy is proposed for the second-order harmonic (H2) reduction. It was implemented and demonstrated using a 0.28-lm thick-oxide MOSFET in 65-nm CMOS process. The NMOS transistor of the conventional antenna switch is replaced with the CMOS transistor composed of an NMOS and PMOS transistor in parallel to improve second-order harmonic distortion (HD2). The optimum channel width of an NMOS and PMOS transistor is chosen to achieve odd symmetry characteristic of I-V curve with respect to the drain-to-source voltage swing (VDS), and, as a result, enhance HD2 of the antenna switch. In addition, the linearity-enhanced biasing scheme is adopted to the PMOS transistor as a conventional negative biasing method of the NMOS transistor. This prevents the degradation of the power handling capability in adopting the PMOS transistor to the antenna switch. In the measurement, the proposed single-stack SPDT antenna switch shows an insertion loss of less than 0.6 dB and an isolation of greater than 38 dB from 100 MHz to 1 GHz with an input and output return loss of greater than 25 dB. Concerning for H2 and third-order harmonic (H3), it shows H2 of -65 dBm and H3 of -90 dBm at 150 MHz when a single-tone RF signal with a power of +5 dBm is applied. Compared to the conventional NMOS-based antenna switch, the proposed CMOS-based antenna switch improves HD2 by approximately 8 dB, 7 dB, and 1 dB at 150 MHz, 400 MHz, and 1 GHz, respectively, while maintaining the comparable insertion loss, isolation, and third-order harmonic distortion (HD3).

A Wideband True Time Delay Circuit Using 0.25 µm GaN HEMT Technology.

This paper presents a wideband 4-bit true time delay IC using a 0.25 μm GaN HEMT (High-Electron-Mobility Transistor) process for the beam-squint-free phased array antennas. The true time delay IC is implemented with a switched path circuit topology using DPDT (Double Pole Double Throw) with no shunt transistor in the inter-stages to improve the bandwidth and SPDT (Single Pole Single Throw) switches at the input and the output ports. The delay lines are implemented with CLC π-networks with the lumped element to ensure a compact chip size. A negative voltage generator and an SPI controller are implemented in the PCB (Printed Circuit Board) due to the lack of digital control logic in GaN technology. A maximum time delay of ~182 ps with a time delay resolution of 10.5 ps is achieved at DC-6 GHz. The RMS (Root Mean Square) time delay and amplitude error are <5 ps and <0.6 dB, respectively. The measured insertion loss is <6.8 dB and the input and output return losses are >10 dB at DC-6 GHz. The current consumption is nearly zero with a 3.3 V supply. The chip size including pads is 2.45 × 1.75 mm2. To the authors' knowledge, this is the first demonstration of a true time delay IC using GaN HEMT technology.

A Fast Surrogate Model-Based Algorithm Using Multilayer Perceptron Neural Networks for Microwave Circuit Design

This paper introduces a novel algorithm for designing a low-pass filter (LPF) and a microstrip Wilkinson power divider (WPD) using a neural network surrogate model. The proposed algorithm is applicable to various microwave devices, enhancing their performance and frequency response. Desirable output parameters can be achieved for the designed LPF and WPD by using the proposed algorithm. The proposed artificial neural network (ANN) surrogate model is employed to calculate the dimensions of the LPF and WPD, resulting in their efficient design. The LPF and WPD designs incorporate open stubs, stepped impedances, triangular-shaped resonators, and meandered lines to achieve optimal performance. The compact LPF occupies a size of only 0.15 λg × 0.081 λg, and exhibits a sharp response within the transmission band, with a sharpness parameter of approximately 185 dB/GHz. The designed WPD, operating at 1.5 GHz, exhibits outstanding harmonics suppression from 2 GHz to 20 GHz, with attenuation levels exceeding 20 dB. The WPD successfully suppresses 12 unwanted harmonics (2nd to 13th). The obtained results demonstrate that the proposed design algorithm effectively accomplishes the LPF and WPD designs, exhibiting desirable parameters such as operating frequency and high-frequency harmonics suppression. The WPD demonstrates a low insertion loss of 0.1 dB (S21 = 0.1 dB), input and output return losses exceeding 30 dB (S11 = −35 dB, S22 = −30 dB), and an output ports isolation of more than 32 dB (S23 = −32 dB), making it suitable for integration into modern communication systems.

A novel design procedure of a compact-size X-band shunt feedback amplifier

ABSTRACT This paper describes a high-frequency shunt feedback amplifier. A new design procedure is presented based on practical design steps as well as theoretical aspects, such as sizing the transistor, stabilisation, and selecting the values of feedback elements. The amplifier is designed and fabricated using 0.15 μm GaAs technology. It operates in the 7–10 GHz frequency range, with a small signal gain of 11.5 ± 0.5 dB and input and output return losses of less than 6 dB and 7 dB, respectively. Furthermore, for 1 dB and 3 dB output compression points, the maximum measured values are 23.1 dBm and 23.9 dBm, respectively. Besides, the maximum measured value for Power Added Efficiency (PAE) for 1 dB output compression is 27.13% and 48.6% for 3 dB output compression. In addition, the measured Noise Figure (NF) in the frequency band of interest ranges from 3.7 to 4.1 dB. The chip area of the fabricated amplifier is 1.01 mm2.

Design and fabrication of a GaN HEMT power amplifier based on hidden Markov model for wireless applications.

Improvement of power amplifier's performance is the desired topic in communication systems. There are many efforts are made to provide good input and output matching, high efficiency, sufficient power gain and appropriate output power. This paper presents a power amplifier with optimized input and output matching networks. In the proposed approach, a new structure of the Hidden Markov Model with 20 hidden states is used for modeling the power amplifier. The widths and lengths of the microstrip lines in the input and output matching networks are defined as the parameters that the Hidden Markov Model should optimize. For validating our algorithm, a power amplifier has been realized based on a 10W GaN HEMT with part number CG2H40010F from the Cree corporation. Measurement results have shown a PAE higher than 50%, a Gain of about 14 dB, and input and output return losses lower than -10 dB over the frequency range of 1.8-2.5 GHz. The proposed PA can be used in wireless applications such as radar systems.

Wideband Multi-Channel Multi-Way Power Combiner With High Frequency Selectivity

A wideband multi-channel multi-way power combiner with high frequency selectivity circuit using the center-loaded multimode step impedance resonator (SIR) is presented in this paper. The SIR stubs can generate four transmission zeros on the both sides of the passbands, which improves the frequency selectivity of the two channels. The distributed coupling technique is used to connect the two different-frequency channels without any additional matching network. The presented power combiner is designed, fabricated, and measured. The measured center frequency and relative 3-dB bandwidth of the two channels are 1.73/2.71 GHz and 43%/35%, respectively. The measured input return loss are greater than 16.4/20.8 dB, the measured output return loss is greater than 20.4/13.4 dB, and the measured insertion loss are 0.7/1.0 dB. Moreover, the measured different-frequency isolation between the two channels is greater than 26.8 dB, and the measured same -frequency isolation are greater than 23.9/29.1 dB, respectively.

Design and fabrication of a Wilkinson power divider with harmonic suppression for LTE and GSM applications

Conventional Wilkinson power dividers (WPDs) can provide acceptable performance close to the nominal center frequency. However, these WPDs can also exhibit poor out-of-band performance while requiring a large footprint. In order to improve on the current state of the art, a modified microstrip WPD is proposed that exhibits a substantially improved stopband and high isolation. A lowpass filter (LPF) structure is utilized in both branches of the power divider to provide harmonic suppression. According to the obtained results, the input return loss (|S11|), output return loss (|S22|), output insertion loss (|S21|) and isolation (|S32|) are better than 34.2 dB, 26.2 dB, 3.52 dB and 31.2 dB, respectively. The proposed modified WPD has a wide 20 dB stopband (from 2.54 GHz to 13.48 GHz) and filters the second to seventh harmonics with attenuation levels of greater than 20 dB. The proposed WPD has a small size of 33.8 mm × 27 mm (0.42 λg × 0.33 λg), where λg is the guided wavelength at the operating frequency of 1.8 GHz. The WPD has been fabricated and tested and shows good agreement between simulated and measured results and the proposed design has desirable characteristics for LTE and GSM applications.

Bandwidth and Stability Improvements of Wideband Receiver Front End Using Inductorless Low Noise Amplifier

The wideband receiver front end composed of a low noise amplifier (LNA) and a bypass path is presented. A conventional current reused LNA with an inductor as a radio frequency (RF) choke is presented to provide reused DC current path. In this brief, the proposed LNA adopts the inductorless circuit topology and the current reused technique to realize compact size, stability condition and bandwidth extension. This receiver front end is fabricated in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.15~{\mu }{\mathrm {m}}$ </tex-math></inline-formula> depletion mode pHEMT technology. The frequency band of the receiver front end is 5-10 GHz, and the chip area is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.6\,\,{\times }\,\,0.5\,\,{{\mathrm {mm}}}^{2}$ </tex-math></inline-formula> . Measured results show that the LNA gain is 21.4-11.5 dB and noise figure (NF) is less than 2.7 dB over 5-10 GHz with 34.3 mW power consumption. For the bypass path, the insertion loss is 1.8-3 dB, and the input and output return loss are better than 10 dB within 5-10 GHz.