A Sub-GHz CMOS SPDT Antenna Switch Employing Linearity-Enhanced Biasing Strategy for Second-Order Harmonic Reduction

Abstract

A CMOS single-pole double-throw (SPDT) antenna switch employing linearity-enhanced biasing strategy is proposed for the second-order harmonic (H2) reduction. It was implemented and demonstrated using a 0.28-lm thick-oxide MOSFET in 65-nm CMOS process. The NMOS transistor of the conventional antenna switch is replaced with the CMOS transistor composed of an NMOS and PMOS transistor in parallel to improve second-order harmonic distortion (HD2). The optimum channel width of an NMOS and PMOS transistor is chosen to achieve odd symmetry characteristic of I-V curve with respect to the drain-to-source voltage swing (VDS), and, as a result, enhance HD2 of the antenna switch. In addition, the linearity-enhanced biasing scheme is adopted to the PMOS transistor as a conventional negative biasing method of the NMOS transistor. This prevents the degradation of the power handling capability in adopting the PMOS transistor to the antenna switch. In the measurement, the proposed single-stack SPDT antenna switch shows an insertion loss of less than 0.6 dB and an isolation of greater than 38 dB from 100 MHz to 1 GHz with an input and output return loss of greater than 25 dB. Concerning for H2 and third-order harmonic (H3), it shows H2 of -65 dBm and H3 of -90 dBm at 150 MHz when a single-tone RF signal with a power of +5 dBm is applied. Compared to the conventional NMOS-based antenna switch, the proposed CMOS-based antenna switch improves HD2 by approximately 8 dB, 7 dB, and 1 dB at 150 MHz, 400 MHz, and 1 GHz, respectively, while maintaining the comparable insertion loss, isolation, and third-order harmonic distortion (HD3).