Output Return Loss Research Articles

On the Coupling Imbalance of the UWB BLC in the 5G Low Noise Amplifier Design

In this article, the design and the development of ultra-wideband UWB branch-line couplers BLCs with a novel method to control the coupling imbalance are proposed. The proposed UWB BLC is suitable for the 5G low-noise amplifier (LNA) design. UWB 4-branch BLC is designed using design curves developed using even and odd mode analyses to cover the 5G (3.3-5 GHz) frequency bands. The vertical branches of the UWB BLC are replaced by modified ones, and their effect on the coupling imbalance is investigated. The proposed BLC occupies an area of 33.9 × 15.7 mm2 Both conventional and modified BLC are fabricated, and their measured S-parameters are compared with analytical and simulated models. Based on the balanced amplifier topology, a 5G UWB low-noise amplifier is designed. The proposed BLCs and the MGF3022AM InGaP-HBT (Heterojunction Bipolar Transistor) are used to produce acceptable UWB performance. The balanced amplifier return loss, noise figure, and gain are investigated as BLCs coupling imbalance varies. The ultra-wideband LNA exhibits an acceptable small-signal gain, noise figure, input return loss, and output return loss across the 5G different frequency bands.

A 60-GHz Variable-Gain Phase Shifter With an Active RL Poly-Phase Filter

A 60-GHz variable-gain phase shifter consisting of an active I/Q generator and Gilbert-cell-based summing amplifier fabricated in a 65-nm bulk CMOS process is presented here. The proposed I/Q signal generator is implemented by inserting an RL poly-phase filter into the interstage node of a cascode amplifier, which provides good interstage matching and results in a finite gain in the I/Q generator. It also provides good isolation characteristics between the I/Q generator and the subsequent vector-summing amplifier due to the common gate buffer stages. Therefore, it minimizes the rms gain and phase errors of the phase shifter by maintaining accurate I/Q signals regardless of the input impedance of the vector-summing amplifier, which varies with the gain and phase states. The vector-summing amplifier is operated by a current-steering digital to analog converter (DAC) to keep the total dc current constant regardless of the gain and phase states, which makes the output return loss constant. The DAC makes the vector-summing amplifier generate an arbitrary vector by determining the sizes of the I and Q vectors, and the double pole, double throw (DPDT) switch determines the quadrants. The rms gain and phase errors of the proposed variable-gain phase shifter show the values of 0.13 dB and 0.36°, respectively, at 60 GHz with 4-bit gain control in a 20-dB dynamic range and 5-bit phase control at 360°. In the 3-dB frequency range of 56.8–64.1 GHz, the rms gain and phase error outcomes are 0.26 dB and 1.44°, respectively. The chip area and overall power consumption are measured and found to be 0.55 mm2 and 14.52 mW, respectively.

A 2.4-GHz Fully-Integrated GaAs pHEMT Front-End Receiver for WLAN and Bluetooth Applications

This paper describes a 2.4-GHz fully-integrated front-end receiver including a single-pole triple-throw (SP3T) switch and a low-noise amplifier (LNA) with bypass function, which was fabricated in a 0.25 μm GaAs pHEMT process. An asymmetrical SP3T switch architecture is incorporated to enable the receiver to operate in four modes. The exploration of impedance and voltage gain behavior of the proposed LNA help to establish the matching network and alleviate the trade-off between noise figure (NF) and gain performance. In LNA high gain mode, the implemented front-end receiver shows 1.7 dB of NF and 6dBm of input third-order intercept point (IIP3) with 20 dB of power gain drawing 11 mA of current from 5 V power supply at 2.4 GHz. All input and output return loss had exceeded 10 dB with fully on-chip impedance matching network. In bypass mode, the measured insertion loss of typically 7.5 dB is achieved.

K 대역 위성통신용 CMOS 저잡음 증폭기 설계

This study entailed the design of a K-band low noise amplifier (LNA) by using the 65-nm bulk CMOS process. In the designed low noise amplifier, a large transistor was used to reduce the size of the lossy gate series inductor, resulting in low noise and high gain. In addition, the source generation and shunt inductors were used at the input stage to enable simultaneous noise and input matching. The LNA had a size of 0.67×0.39 mm2 including RF and DC pads. A peak gain of 19.5 dB and a minimum noise figure of 2.31 dB were achieved. Owing to the design, the input and output return loss was more than 10 dB at 17~23 GHz.

Design of 2–16 GHz Non-Uniform Distributed GaN HEMT MMIC Power Amplifier with Harmonic Suppression Network

In this paper, an ultra-wideband (UWB) power amplifier (PA) on a 0.25 μm gallium-nitride (GaN) on silicon carbide (SiC) high-electron-mobility transistor (HEMT) process, operating in Ku-band, is presented. The broadband PA design is based on the four-stage non-uniform distributed amplifier structure. In order to improve the efficiency of the PA, a harmonic suppression network is added at the output of the drain artificial transmission line. At the same time, a capacitor is connected in series at the input of the gate, which is used to compensate for the phase offset of the gate and increase the cut-off frequency of the PA. The final gate width of the first stage is 0.56 μm, and the other three-stage gate widths are all 0.32 μm. Over the frequency range of 2–16 GHz, the simulated results of this NDPA exhibit a power-added efficiency (PAE) of 16.6–27%, a saturated continuous wave (CW) output power of 35–37 dBm, a small signal gain of 9.1–11.6 dB, and output return losses of 5–15 dB.

An Inductorless Gain-Controllable Wideband LNA Based on CCCIIs.

In this paper, an inductorless and gain-controllable 0.5~2.5 GHz wideband low noise amplifier (LNA) based on second generation current controlled current conveyors (CCCIIs) is presented. The proposed wideband LNA utilizes CCCIIs as building blocks to implement the amplifier stage and impedance matching stage. By varying the DC biasing current of the CCCII, the voltage gain of the proposed LNA is controllable in the range of 1~18 dB. In the frequency range of 0.5~2.5 GHz, the post-layout simulation results show that the proposed LNA has a typical voltage gain S21 of 12.6 dB with a gain ripple of ±1.5 dB, an input and output return loss (S11 and S22) of, respectively, -21.4 dB to -16.6 dB and -18.6 dB to -10.6 dB, and a high reverse isolation S12 of -65.2 dB to -39.5 dB. A noise figure of 4.05~4.35 dB is obtained across the whole band, and the input third-order intercept point (IIP3) is -2.5 dBm at 1.5 GHz. Using a 0.18 μm RF CMOS technology, the LNA occupies an active chip area of only 0.096 mm2 with a power consumption of 12.0 mW.

A 7–13 GHz 10 W High-Efficiency MMIC Power Amplifier in 0.25 µm GaN HEMT Process

With the increase in applications of the millimeter wave spectrum for phased array radar systems, mobile 7–13 communication systems, and satellite systems, the demand for a wideband, high-efficiency, high-power monolithic microwave integrated circuit (MMIC) power amplifier (PA) is increasing. In this paper, a 7–13 GHz 10 W high-efficiency MMIC PA is designed. This amplifier consists of a two-stage circuit structure with two high electron mobility transistor (HEMT) cells for the driver stage and four HEMT cells for the power stage. To ensure high efficiency and a certain output power (Pout), both the driver–stage and power–stage transistors use a deep Class–AB bias. At the same time, in order to further improve the efficiency, low-loss and second–harmonic tuning techniques are used in the output and inter-stage matching networks, respectively. Finally, the electromagnetic simulation results show that within a frequency of 7–13 GHz, the amplifier achieves an average saturated continuous wave (CW) Pout of 40 dBm, a small signal gain of 14.5–15.5 dB, a power-added efficiency (PAE) of 30–46%, and the input and output return loss are better than 5 dB and 8 dB, respectively.

Millimeter-Wave Wideband Differential Four-Way Wilkinson Power Divider With 90° Rotational Symmetric Layout

This letter presents a four-way millimeter-wave differential Wilkinson power divider (WPD) with broadband characteristics using multisectional coupled inductors. To reduce the size effectively, one of the inductors is placed in a common path and the others in differential paths, which are mutually coupled with each other. It has a 90° rotational symmetric layout to minimize amplitude mismatches between channels. It shows a minimum insertion loss (IL) of 1.1 dB at 24 GHz and a peak isolation of 30 dB at 44 GHz. Over 20–44 GHz (~75% bandwidth), it also shows an IL of less than 1.8 dB and an isolation of greater than 14.5 dB. The measured input and output return losses show greater than 8 and 13.2 dB, respectively, in 20–44 GHz. The core chip is 0.35 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times \,\, 0.41$ </tex-math></inline-formula> mm and is fabricated using a 65-nm RF CMOS process.

Design and Simulation of Equal Split Wilkinson Power Divider İremnur Duru1

In this study, the design and simulation of an equally split C Band Wilkinson Power Divider is presented. It is aimed that the divider distributes the power equally and provides lossless, reciprocal, and high isolation between the output ports. Microstrip technology has been utilized as the design process. A micro strip is a transmission line mounted on a copper conductive material. It has been used 𝜆/4 transformer with characteristic impedance 2 ∙ 𝑍0. In this system, improvements have been made to increase bandwidth and high isolation. The designed divider has been simulated in the AWR Microwave Office. It has been used FR4 substrate with 0.21 mm thickness. Operating frequency has been chosen 7.2 GHz. The designed divider is suitable for good matching and isolation according to S parameter values. While the S21 and S31 values should be -3 dB in theory, it is not possible for us to see this value in the designed systems. From the simulation results, Insertion Loss (S21 and S31), Isolation Loss (S32) are about -3.4 dB, -22 dB respectively. Input (S11) and Output return loss (S22) are respectively about -22 dB and -44 dB. The designed power divider is a passive circuit element used to divide power at the same or different frequencies in mobile and small applications. The simulated power divider has useful in RF applications.

A Self-Equalized Linear-Phase Absorptive BPF Using Negative-Group-Delay Admittance Inverters

In this letter, a microstrip negative-group-delay (NGD) admittance inverter (J-inverter) is proposed to implement a self-equalized linear-phase absorptive bandpass filter (ABPF). It is revealed that this NGD J-inverter, being composed of a coupled-line loaded with a lumped resistor and an open-circuited stub, has an NGD pit in its frequency response. The superposition of the NGD pits associated with a specific number of the NGD J-inverters is utilized to counterbalance the group delay (GD) peaks at the lower and upper edge of the ABPF passband. A three-order ABPF prototype with a passband of 1.5–2.5 GHz is designed using six NGD J-inverters. Measured GD fluctuation within the 3-dB bandwidth is reduced to 0.18 from 0.59 ns compared with the ABPF using the conventional <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\lambda $ </tex-math></inline-formula> /4 J-inverter. The sharpness of the out-band roll-off has been retained. The measured input–output return loss is better than 12 dB over 0.6–3.5 GHz.

A Compact 6-bit Phase Shifter in 65 nm RF CMOS Technology for ISM Band

We presented a 6-bit switched-network type phase shifter, which was implemented in Samsung 65nm RF CMOS technology. The phase shifter was designed with lumped-element filter topologies using inductors and capacitors for compact size. For 64 states, in the frequency of 2.12 GHz - 2.51 GHz, measured insertion loss was -9.7±1.5 dB. The input and output return loss were above 8.2 dB and 10 dB, respectively. The rms phase error and rms amplitude error were less than 3° and 0.87 dB, respectively. The chip size with including pads was 1.4 × 0.81 mm².

Design of Wilkinson power divider at 28 GHz for 5G applications

A power divider &lt;span&gt;plays a significant function in antenna’s feeding network. Many types of power divider exist yet there are only a few existing studies of Wilkinson power dividers at high frequencies (28 GHz) for 5G communications systems. This paper presents a tapered 2-way Wilkinson power divider that operates in Malaysia's 5G wireless communication band (28 GHz). CST microwave studio is used to design, simulate, and optimize the tapered 2-way Wilkinson divider. The simulation results show resonance around 23.5-37.9 GHz. The operating frequency of 28 GHz resulted in power division with a 3.2 dB insertion loss and has an isolation of 19.21 dB. The design can be made wideband with equal power division at each output port by adding an extra resistor along the tapered line to reduce output return loss and isolation, as demonstrated in this paper.&lt;/span&gt;

DC Power-Optimized Ka-Band GaN-on-Si Low-Noise Amplifier With 1.5 dB Noise Figure

A <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Ka</i> -band low-noise amplifier for low-consumption robust receivers is presented in this letter. The monolithic microwave integrated circuit (MMIC) is designed on a 100 nm GaN-on-Si technology provided by OMMIC foundry and decibel gain, average noise figure (NF) of 1.5 dB, with input–output return losses better than 15 dB in the whole 27–31 GHz design band. Large signal measurements show a OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1 dBcp</sub> of +16 dBm and survivability to RF input power verified up to +25 dBm without showing critical degradation. These performances have been achieved with only 150 mW dc power consumption in linear operating condition, 30% less than other <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Ka</i> -band GaN LNAs published in the open literature.

Compact Ku‐band CMOS ×3 frequency multiplier with improved harmonic suppression

This study presents a Ku-band ×3 frequency multiplier implemented using the 65 nm CMOS process. A frequency tripler core consisting of a single-ended structure is employed to achieve a small size. A high-pass filter and a notch filter are used in the output matching network to overcome the low harmonic suppression of the single-ended structure. Furthermore, an input variable gain amplifier, a frequency tripler core, and an output variable gain amplifier are used in the ×3 frequency multiplier structure to achieve high conversion gain and harmonic suppression. The size of the ×3 frequency multiplier is 0.8 × 0.9 mm2. Measurement results show that the conversion gain for the 15.99–17.52 GHz range is 1.53–24.81 dB at input power values of –20, –25, and –30 dBm, and the harmonic suppression is greater than 24.29–34.71 dBc. In the operating frequency band, the input and output return losses are greater than 10 dB, and the power consumption is 15–18 mW.

A Wideband High-Efficiency GaN MMIC Power Amplifier for Sub-6-GHz Applications.

The monolithic microwave integrated circuit (MMIC) power amplifiers serve an essential and critical role in RF transmit/receive (T/R) modules of phased array radar systems, mobile communication systems and satellite systems. Over recent years, there has been an increasing requirement to develop wideband high-efficiency MMIC high power amplifiers (HPAs) to accommodate wideband operation and reduce power consumption. This paper presents a wideband high efficiency MMIC HPA for Sub-6-GHz applications using a 0.25-μm gate-length D-mode GaN/SiC high electron mobility transistor (HEMT) process. The amplifier consists of two stages with two HEMT cells for the driver stage and eight HEMT cells for the power stage. To obtain a flat gain while maintaining the wideband characteristic, a gain equalization technique is employed in the inter-stage matching circuit. Meanwhile, a low-loss output matching network is utilized to ensure high efficiency. The fabricated HPA occupies a compact chip area of 14.35 mm2 including testing pads. Over the frequency range of 2–6 GHz, measured results of this HPA show a saturated continuous wave (CW) output power of 44.4–45.2 dBm, a power added efficiency (PAE) of 35.8–51.3%, a small signal gain of 24–25.5 dB, and maximum input and output return losses of 14.5 and 10 dB, respectively.

A Full Ka-Band CMOS Amplifier Using Inductive Neutralization with a Flat Gain of 13 ± 0.2 dB

This paper presents a CMOS wideband amplifier operating in the full Ka-band, with a low gain variation. An inductive neutralization is applied to the amplifier to compensate for the gain roll-off in the high-frequency region. Neutralization inductance is carefully determined considering the tradeoff between stability and gain. To achieve a low gain variation over the full Ka-band, the amplifier employs the frequency staggering technique in which impedance matching for three gain stages is performed at different frequencies of 26, 34, and 42 GHz. The experimental results show that a peak gain of 13.2 dB is achieved at 39.2 GHz. The 3 dB bandwidth is from 23.5 to 41.7 GHz, which fully covers the Ka-band. Especially, the gain ripple of the amplifier is only 13 ± 0.2 dB over a wide bandwidth from 26.2 to 40.2 GHz. The input and output return loss values are better than −10 dB from 26.3 to 40.1 GHz and from 25.3 to 50 GHz, respectively. The DC power consumption is 18.6 mW.

An S/C/X-Band 4-Bit Digital Step Attenuator MMIC with 0.25 μm GaN HEMT Technology

In this paper, a 4-bit digital step attenuator using 0.25 μm GaN HEMT technology for wideband radar systems is presented. A switched-path attenuator topology with resistive T-type attenuators and double-pole double-throw (DPDT) switches was used to achieve both low insertion loss and phase/amplitude error. The measured insertion loss of the reference state is 2.8–8.3 dB at DC-12 GHz. The input and output return loss are less than 12 dB at DC-12 GHz. An attenuation coverage of 30 dB with a least significant bit of 2 dB was achieved at DC-12 GHz. A root mean square (RMS) amplitude error of 1 dB and a phase error of 8.5° were achieved, respectively. The attenuator chip size is 2.45 mm × 1.75 mm including pads. To the best of the authors’ knowledge, this is the first demonstration of a GaN-based digital step attenuator.

Design of a Source Degenerated Cascode Stage Low Noise Amplifier for 5G Applications

Low Noise Amplifier (LNA) is the most critical part of a receiver front end in terms of the receiver performance. The performance tradeoff among input matching, noise figure, gain, and linearity are analyzed in detail. The LNA finds its application at Portable GPS Receiver, BLE, Zigbee, NFC, WiFi, Wireless Sensor Network, RFIC operating at 2.4GHz frequency. Millimeter wave communication is an evolving technology for bandwidth demanding 5G wireless application. A high gain and linear narrowband cascode Low Noise Amplifier (LNA) operating at 2.18GHz to 2.47GHz is proposed. To demonstrate design methodology, a narrow-band source degenerated cascode LNA is designed and simulated in a standard 90nm CMOS process to operate in the 2.4 GHZ band. The LNA achieves a voltage gain of 5.38dB, Noise figure of 4.1127dB, and from 3.2 V supply voltage. Proper input and output impedance matching have been performed to achieve the input return loss of -14 dB (S11) and output return loss of -19.72 dB (S22). Simulation study has been done using Cadence spectre.

Low‐insertion‐loss planar four‐way Gysel power divider with high isolation employing two‐layer substrates

AbstractThis paper presents a kind of novel planar four‐way Gysel power divider that has high isolation and low insertion loss (IL). This power divider adopts two‐layer substrates. The power divider circuit and isolation circuit are on different layers. For analysis and design, an equivalent circuit is given. The relationship between the impedance of the matching section and the working bandwidth is analyzed. The design process is given to illustrate a specific method that also applies to the N‐way Gysel power divider. For verification, a prototype is designed, manufactured. The measured results show that IL is 6.3 ± 0.1 dB approximately. The 20 dB relative isolation bandwidth achieves 45%. Between 1.88 and 2.64 GHz, the input return loss (RL) achieves 15 dB. And between 1.78 and 2.75 GHz, the output RL is better than 15 dB.

Design of 2.4 GHz LNA of 400 MHz Bandwidth

Low Noise Amplifier (LNA) is the most important front-end block of the receiver. LNA’s Noise figure (NF) and Scattering Parameters affect the overall performance of the whole receiver circuit. Nowadays in the era of 5G technology, The quality of data that is being transmitted is increased. So there is a need for higher bandwidth to transfer data with higher speed. In such a case, communication blocks need an update. The research is carried out for the advancement of the LNA. The primary goal of LNA design is to lower the Noise Figure and return losses. The paper aims to design a 2.4 GHz LNA having a bandwidth of 400 MHz. The circuit is designed with the help of single-stub microstrip lines. We tried to keep the length of microstrip lines as minimum as possible. The transistor ATF-21170 Gallium Arsenide Field Effect Transistor (GaAs FET) is used in this work. The circuit is simulated in the Keysight Advance Design System (ADS). The amplifier is manually designed using standard methods. LNA is unconditionally stable for the frequency range of 2.2 GHz to 2.6 GHz. To build impedance matching circuits of the amplifier smith chart is used. It is observed that the LNA gain (S21) is greater than 15.3 dB, NF less than 1.2 dB, Input return loss (S11) is less than -13.3 dB, Output return loss (S22) is less than -17.1 dB over the 400 MHz bandwidth ranging from 2.2 to 2.6 GHz. This has, to the best of the authors' knowledge, not been presented in literature before.