K 대역 위성통신용 CMOS 저잡음 증폭기 설계

Abstract

This study entailed the design of a K-band low noise amplifier (LNA) by using the 65-nm bulk CMOS process. In the designed low noise amplifier, a large transistor was used to reduce the size of the lossy gate series inductor, resulting in low noise and high gain. In addition, the source generation and shunt inductors were used at the input stage to enable simultaneous noise and input matching. The LNA had a size of 0.67×0.39 mm2 including RF and DC pads. A peak gain of 19.5 dB and a minimum noise figure of 2.31 dB were achieved. Owing to the design, the input and output return loss was more than 10 dB at 17~23 GHz.