Compact Ku‐band CMOS ×3 frequency multiplier with improved harmonic suppression

Abstract

This study presents a Ku-band ×3 frequency multiplier implemented using the 65 nm CMOS process. A frequency tripler core consisting of a single-ended structure is employed to achieve a small size. A high-pass filter and a notch filter are used in the output matching network to overcome the low harmonic suppression of the single-ended structure. Furthermore, an input variable gain amplifier, a frequency tripler core, and an output variable gain amplifier are used in the ×3 frequency multiplier structure to achieve high conversion gain and harmonic suppression. The size of the ×3 frequency multiplier is 0.8 × 0.9 mm2. Measurement results show that the conversion gain for the 15.99–17.52 GHz range is 1.53–24.81 dB at input power values of –20, –25, and –30 dBm, and the harmonic suppression is greater than 24.29–34.71 dBc. In the operating frequency band, the input and output return losses are greater than 10 dB, and the power consumption is 15–18 mW.