Output Return Loss Research Articles

Printed Circuit Board Implementation of N-Way Power Combiner With Isolated Input Ports

A planar implementation of N-way radial power combiners with isolated input ports is presented. While keeping the design simple, the presented combiner can be manufactured solely using printed circuit board technology, and as a result, has a low weight and manufacturing cost. As proof of concept, two power combiners are designed and built. First, a 6-way combiner working at the center frequency of 3.1 GHz with a fractional bandwidth of around 30% was designed. Our measurements of the fabricated combiner showed an input and output return loss of better than 10 dB in a frequency band of 2.65-3.55 GHz where an isolation of higher than 23 dB, amplitude balance of ±0.1 dB, and phase balance of ±1 degree between the input ports were obtained. Then, a simple approach was implemented to widen the frequency band, achieving a fractional bandwidth of 80%. According to our measurements, the wideband combiner has an operating frequency band of 1.35-3.15 GHz, in which an input and output return loss of better than 10 dB with an isolation of higher than 21 dB, amplitude balance of ±0.15 dB, and phase balance of ±1 degree were achieved.

A 23 dBm Gain Shaping Stacked Power Block CMOS Power Amplifier Achieving 36% PAE

This paper introduces a design methodology that reduces the fundamental trade-off between linearity and power added efficiency (PAE) in CMOS power amplifier (PA). In our work, a stacked power block (SPB) has been proposed to mitigate the effect of gate–source capacitance (Cgs), thus linearizing the PA. Each stage is biased independently to shape the gain profile, either to be in the expanded mode or in the compressed mode, in which once combined it delivers a flat gain response and confirming the linearity performance. Efficient PI input and output matching networks are proposed to ensure no further distortion, once connected to the 50 Ω source and load. The PA achieves input and output return losses of less than −10 dB from 2.40 to 2.50 GHz. At the center frequency of 2.45 GHz, the SPB-PA achieves a gain of 10 dB and it is unconditionally stable. The proposed gain shaping linearization technique delivers a maximum linear output power (Poutlinmax) of 19.8 dBm with only 3.3 dB back-off from maximum output power (Poutmax) of 23.1 dBm. The SPB-PA meets the WLAN specification with linear PAE of 30% and peak PAE of 36.1%. The proposed SPB-PA reduces the fundamental trade-off between linearity and efficiency. Integration of this PA in wireless SoC shall reduce the chip’s overall power consumption.

The Development of Cascode Low Noise Amplifier with Double Feedback Technique Architecture for Wireless Communication

The paper aims to develop a new cascode low noise amplifier (LNA) by using double feedback technique architecture for wireless communication especially for long term evolution (LTE). The objective of this article is to display the improved performance of gain by minimizing noise figures with innovative techniques for the realization of Long Term Evolution (LTE). The innovation technique with implementation double feedback technique architecture outlines the possibility to improve the performance in various parameters such as bandwidth, stability, gain, noise figure, power consumption and complexity. The realization using cascode LNA is verified by using FHX76LP Super Low Noise HEMT that operate at 5.8 GHz in compliant with LTE standard. The Advance Design System (ADS) software is used to obtain characteristics for collecting data in a smith chart and s-parameter generated by simulation. The cascode LNA with the double feedback technique achieves an average gain of 20.887 dB with a noise figure of 0.341 dB. The input return loss and output return loss are – 14.354 dB and – 11.879 dB respectively. The outcome of this work will contribute to providing a better wireless signal receiver especially for the LTE standard and it potentially addressing wireless communication issues in rural areas.

A Novel Analytical Design Technique for a Wideband Wilkinson Power Divider Using Dual-Band Topology.

In this paper, a novel analytical design technique is presented to implement a coupled-line wideband Wilkinson power divider (WPD). The configuration of the WPD is comprised of three distinct coupled-line and three isolation resistors. A comprehensive theoretical analysis is conducted to arrive at a set of completely new and rigorous design equations utilizing the dual-band behavior of commensurate transmission lines. Further, the corresponding S-parameters equations are also derived, which determine the wideband capability of the proposed WPD. To validate the proposed design concept, a prototype working at the resonance frequencies of 0.9 GHz and 1.8 GHz is designed and fabricated using 60 mils thick Rogers’ RO4003C substrate. The measured result of the fabricated prototype exhibits an excellent input return loss > 16.4 dB, output return loss > 15 dB, insertion loss < 3.30 dB and a remarkable isolation > 22 dB within the band and with a 15 dB and 10 dB references provide a fractional bandwidth of 110% and 141%, respectively.

Design of Ka-band broadband low-noise amplifier using 100nm gate-length GaN on silicon technology

Due to the high breakdown voltage and better linearity of gallium nitride (GaN) high electron mobility transistor (HEMT), GaN based RF front-end is widely researched and studied. In this paper, a Ka-band cascode low-noise amplifier (LNA) designed with 100nm gate-length GaN-on-silicon technology is presented. With novel methods such as the introduction of high-pass filters and standing wave filtering capacitors, the LNA achieves a stable gain of 21-22.8dB and a noise figure (NF) of 0.9-1.3dB from 22GHz to 38GHz. The input and output return loss are better than-10dB in band of concern. This LNA occupies an area of 2.3mm × 0.9mm and consumes 265-mW DC power. Compared with silicon-on-insulator (SOI), indium phosphide (InP) and gallium arsenide (GaAs) LNAs, the proposed GaN LNA exhibits better performance of linearity, as well as competitive gain and NF.

Design and performance analysis of low power LNA with variable gain current reuse technique

This paper presents a CMOS low power Variable Gain Low Noise Amplifier for 26–34 GHz in 45 nm process technology, which composes of cascaded complimentary common gate (CCG) stage and digital current steering amplifier. First stage is CCG stage, which helps in achieving the low power consumption and less area. Second stage is variable gain amplifier, uses current reuse technique as well as gm-boost technique and has constant dc current to make the input impedance stable. Source degeneration technique cancel out MOS parasitic capacitance help in achieving linearity. Simulated maximum peak gain is 13.139 dB at 30.57 GHz and lowest peak gain is 7.75 dB at 26 GHz i.e. approximately flat over the entire band. Lowest NF is 3.08 dB at 32.6 GHz. Process corner simulation has been done for all four corners (S–S, S–F, F–S, F–F) showing robustness of LNA. Input return loss has value less than − 9.58 dB while output return loss has less than − 2.6 dB showing good matching; power consumption is 16 mW for dc current of 16 mA at 1 V. MOS active chip area is 76.727 µm2.

Optimization of spaceflight millimeter-wave impedance matching networks using laser trimming

AbstractRealizing packaged state-of-the-art performance of monolithic microwave integrated circuits (MMICs) operating at millimeter wavelengths presents significant challenges in terms of electrical interface circuitry and physical construction. For instance, even with the aid of modern electromagnetic simulation tools, modeling the interaction between the MMIC and its package embedding circuit can lack the necessary precision to achieve optimum device performance. Physical implementation also introduces inaccuracies and requires iterative interface component substitution that can produce variable results, is invasive and risks damaging the MMIC. This paper describes a novel method for in situ optimization of packaged millimeter-wave devices using a pulsed ultraviolet laser to remove pre-selected areas of interface circuit metallization. The method was successfully demonstrated through the optimization of a 183 GHz low noise amplifier destined for use on the MetOp-SG meteorological satellite series. An improvement in amplifier output return loss from an average of 12.9 dB to 22.7 dB was achieved across an operational frequency range of 175–191 GHz and the improved circuit reproduced. We believe that our in situ tuning technique can be applied more widely to planar millimeter-wave interface circuits that are critical in achieving optimum device performance.

Wave discrimination at C-band frequencies in microstrip structures inspired by electromagnetically induced transparency

We present the design and practical implementation of a microstrip diplexer based on the wave discrimination property associated with the electromagnetically induced transparency (EIT)-like effect. The EIT is a quantum interference phenomenon which happens between two atomic transition pathways and allows wave propagation within a medium’s absorption spectrum. Here, we exploit an analogous interference mechanism in a three-port microstrip structure to demonstrate a diplexer based on the EIT-like effect in the microwave regime. Since the transparency is accompanied by a high transmission and strong dispersion characteristics, compact frequency discriminating structures that can resolve nearby frequencies with high isolation can be devised. Our proposed C-band diplexer consists of pairs of unequal open-circuit stubs, which resonate at detuned frequencies and interfere to form the EIT-like passbands for diplexer action. The design is highly compact and scalable in frequency for both PCB and on-chip applications. A prototype of diplexer is fabricated for the center frequencies of lower and upper passbands at 4.6 GHz and 5.5 GHz respectively. The transmission zeros are designed at the complementary channels so that the two passbands are highly isolated presenting the isolation of about 40 dB. The measured insertion loss of lower and upper passband is 0.59 dB and 0.61 dB respectively. Measured input return loss is better than − 15 dB, while the output return losses are well below − 12 dB. Moreover, a decent value of about 200 is achieved for the group refractive index around the EIT-like passbands, which reveals the slow wave characteristics of the proposed EIT-based diplexer.

Cascode Low Noise Amplifier (LNA) with Negative Feedback for Long Term Evolution (LTE)

Every now and then communication technology continuing to evolved to fulfil the market especially in mobile traffics of wireless technology demanding for high-rise data rates affecting radio frequency bandwidths to affirming specific performance. Utilizing unlicensed bandwidths of 5.8 GHz, the cascode low noise amplifier (LNA) enable to associate with long term evolution (LTE) standard without detracting degradation of service aspects. Considering LNA that positioned as a front-end in receiver block system in managing transmit the signal it benefit the LTE RF requirement become novelty in this design that plays crucial role. This paper focuses on designing and analysis of cascode low noise amplifier (LNA) adopted negative feedback and T-matching network at the input and output ports to emphasize trade-offs between parameters of gain, noise figure, sensitivity and stability. Pseudomorphic High Electron Mobility Transistor (PHEMT) FHX76LP manufactured by Eudyna Devices Inc is selected and the design is stimulated by using Advance Design System tool (ADS). From the analysis resulting LNA shows a maximum gain (S21) of 20.199 dB and return loss (S12) of −23. 585 dB with minimum noise figure of 0.360 dB with 2V supply. Meanwhile, the input reflection (S11) and output return loss (S22) are −11. 101 dB and −13. 714 dB respectively.

Active Inductor-Based Ultra-Wideband Low Noise Amplifier for Rejection of Wireless LAN Interference

This paper presents a low noise amplifier (LNA) for the ultra-wideband (UWB) application in the range 3.1–10.6 GHz based on active inductor topology. The LNA is designed to provide a flat gain and to reject wireless local area networking interference at 5–6 GHz band. An active inductor based on the feedback resistor topology is proposed in this work and integrated with the LNA. The use of an active inductor instead of a conventional CMOS spiral inductor provides advantages over the area, quality factor, and inductance. The active inductor provides a relatively uniform inductance at 5–6 GHz and is used to design an on-chip notch filter circuit, which achieves a maximum attenuation of 45 dB at the center frequency of ~5.6 GHz. The LNA is designed and processed in the standard 0.18 mm CMOS technology. The simulated LNA exhibits the gain of 20 dB and a noise figure of less than 3.7 dB in the non-interfering bands. The input (S11) and output return losses (S22) are less than –10 and –12 dB, respectively, in the allocated UWB frequency spectrum, and amplifier occupies a chip area of 0.54 µm2. The proposed LNA has a superior flat gain, excellent interference rejection, minimum return losses, and a low noise figure in the intended operation band. This LNA finds important application in the radiofrequency front-end devices for UWB application.

A Fully Integrated Arbitrary Power Divider on Printed Circuit Board by a Novel SMD-Resistor-Free Isolation Network

An arbitrary power divider (PD), which can be fully integrated on a multilayered printed circuit board (PCB), is presented without using the surface-mounted device (SMD) resistors. In the proposed SMD-resistor-free isolation network, a new multiple microstrip gap-coupled resonators (MM-GCRs) is designed in an FR4 substrate based on an optimization algorithm to achieve an equivalent grounded resistor in the desired frequency band. Consequently, the acquired output matching and isolation bandwidths are designable and much wider than that of other existing SMD-resistor-free PDs with both output matching and isolation characteristics. To verify it, the design of PCB-based SMD-resistor-free PDs with the power division ratio being 1–3 is given. For all fabricated PDs, the measured input return loss and extra insertion loss are, respectively, better than 20 dB and less than 0.52 dB, respectively, at the operating frequency. In addition, the measured output return loss and isolation loss are better than 15 dB from 2.4 to 2.5 GHz. Moreover, the measured output matching and isolation bandwidths are, respectively, 8 and 3.5 times wider than that of other existing SMD-resistor-free PD with both output matching and isolation characteristics. Since the proposed PD is synthesized based on distributed elements without using any SMD resistor, the proposed PD thus possesses the advantages of being suitable for system-on-package (SoP), cost-efficient, suitable for millimeter-wave (mm-Wave) application, and capable to be fully integrated on a multilayered PCB.

A 27‐33 GHz compact medium power amplifier with pole‐tuning technique in 130 nm CMOS technology

AbstractThis article proposes a 27‐33 GHz compact medium power amplifier with pole‐tuning technique in 130 nm CMOS technology. The resonant frequencies of three stages are arranged appropriately by pole‐tuning technique to achieve wide bandwidth. π‐type network is employed for input matching and L‐type network is used for output matching. The measured results show the proposed amplifier has a peak gain of 12.5 dB at 30.2 GHz and a bandwidth of 6 GHz. The amplifier delivers an input 1‐dB gain compression point (IP1dB) of −4 dBm and a saturated output power (PSAT) of 11.7 dBm at 30 GHz. It consumes 42.72 mW with a core area of 412 × 215 μm2 and the input and output return losses are better than −10 dB.

A Digital Controlled Accurate Linear-in-dB Variable Gain Amplifier Based on Current-Steering Structure with Compensation Circuit

The paper proposes a radio frequency front-end ultra-wideband variable gain amplifier (VGA) which is based on improved current-steering topology. The design is implemented in Tower Jazz 0.18 μm SiGe BiCMOS technology. Adding the gain compensation circuit broadens gain dynamic range, and introducing the emitter degeneration capacitor broadens the bandwidth of a typical current-steering topology. Moreover, the digital control function is obtained from the digital-to-analog converter circuit. Also, the input and output matching circuits are designed for testing. The measurement results show that the designed VGA achieves a gain dynamic range of 31 dB stepped by 1 dB from 8 to 18 GHz. Furthermore, input and output return losses are both lower than − 10 dB, and output 1 dB compression point is − 19.6 dBm ~ − 17 dBm at the highest gain stage. The VGA’s DC power consumption is about 14 mA from a 3.3 V supply, and it occupies a chip area of just 0.56 mm2.

Design and Analysis of 2.4 GHz Low-Noise, High-Gain 0.18 μm CMOS Cascode Low-Noise Amplifier for IRNSS Applications

Low-Noise Amplifier (LNA) plays a crucial part in Radio Frequency (RF) front-end architecture. This paper mainly focuses on designing LNA for Indian Regional Navigation Satellite System (IRNSS) receiver. IRNSS operates on two frequency bands (L5 and S band) and this design is proposed for S band with the center frequency of 2492.028 MHz. Cascode topologies are considered to be conventional ones and they provide higher gain and better reverse isolation. Four different approaches of single-stage cascode topology, such as Common Source (CS) cascode, Common Gate (CG) cascode, shunt-resistive feedback cascode and current reuse cascode, were designed and their performance metrics, based on gain, Noise Figure (NF), return losses and stability, are presented. Focused on the gain and noise figure improvements, Common Source (CS) cascode with interstage series LC circuit LNA was designed and optimized with input and output matching circuitries. The proposed optimized circuit uses current reuse technique along with CS stage to improve the power gain and to achieve low-noise figure. The interstage LC circuit is mainly implemented to act as a tuning circuit to achieve a narrow range of frequency. The proposed work is simulated using 180 nm CMOS technology Generic Process Design Kit (GPDK) and achieve a power gain (S21) of 24.89, 0.994 dB NF, −16.2 dB input return loss (S11) and −11.06 dB output return loss (S22), with higher reverse isolation around −30.47 dB at 1.8 V power supply.

A 0.1–1.5 GHz multi-octave quadruple-stacked CMOS power amplifier

In this letter, we design and analyze 0.1–1.5 GHz multi-octave quadruple-stacked CMOS power amplifier (PA) in 0.18 μm CMOS technology. By using two-stage quadruple-stacked topology and feedback technology, the proposed PA realizes an ultra-wideband CMOS PA in a small chip area. Wideband impedance matching is achieved with smaller chip dimension. The effects of feedback resistors on the RF performance are also discussed for this stacked-FET PA. The PA shows measured input return loss (< –10.8 dB) and output return loss (< –9.6 dB) in the entire bandwidth. A saturated output power of 22 dBm with maximum 20% power added efficiency (PAE) is also measured with the drain voltage at 5 V. The chip size is 0.44 mm2 including all pads.

A 1.7-dB Minimum NF, 22–32-GHz Low-Noise Feedback Amplifier With Multistage Noise Matching in 22-nm FD-SOI CMOS

A low-noise feedback amplifier (LNA) with interstage noise matching is implemented in 22-nm fully depleted silicon-on-insulator (SOI)-CMOS technology. Minimum noise figure (NF) is 1.7 dB centered at 28 GHz, and NF remains below 1.98±0.25 dB across a 10-GHz range. Peak gain of the two-stage LNA is 21.5 dB at 22 GHz, and the bandwidth (BW) for $|{S_{21}} |$ is 19–36 GHz. Input and output return losses are better than 10 dB across an effective LNA BW of 22–32 GHz. The third-order input intercept is −13.4 dBm at peak gain when dissipating 17.3 mW. Continuous dc power control on the fly is implemented using modulation of FET backgates. When dc power consumption is reduced 5.6 mW, NF increases by less than 0.5 dB, peak gain decreases by 3.6 dB, and input return loss remains better than 10 dB with no change in effective BW.

Single-Layer Dual-Band Balanced Substrate- Integrated Waveguide Filtering Power Divider for 5G Millimeter-Wave Applications

A single-layer substrate-integrated waveguide (SIW) filtering power divider (FPD) with fully differential operation at 28 and 39 GHz is proposed in this letter. This FPD consists of three SIW cavities where the differential and common modes of each cavity were properly designed to form three-pole dual passbands, facilitate deployment of isolation resistors, and introduce transmission zeros while attaining high in-band common-mode rejection. To improve the output return loss and isolation in dual bands, a novel and simple approach to find the proper location of isolation resistors is presented. At operating frequencies, the measured differential-mode input or output return loss, minimum insertion loss, isolation, and common-mode suppression are >14.1 dB, 14.9 dB, and >30.3 dB, respectively. The amplitude and phase imbalances between outputs are < 0.48 dB and <4.2°, respectively.

A Compact Ka-Band 4-bit Phase Shifter With Low Group Delay Deviation

This letter presents a compact $Ka$ -band 4-bit switch-type phase shifter with low group delay deviation (GDD) using 28-nm CMOS technology. A magnetically coupled all-pass network (APN) configuration is employed to achieve both equal and flat group delay characteristics versus frequency at each phase state. The measured rms phase error is 1.2°, and the gain error is 1.1 dB at 33 GHz. The average measured insertion loss is 12.8 dB at 33 GHz, and the input and output return losses are both lower than −10 dB from 29 to 37 GHz. The fabricated phase shifter has a compact size of 0.08 mm2 excluding pads, low GDD of ±4 ps, and rms group delay error of $Ka$ -band phase shifter has the lowest GDD per bandwidth (GDD/BW) compared with other reported passive phase shifters.

Modified Wilkinson power divider with harmonics suppression and compact size for GSM applications

In this article, a modified microstrip Wilkinson power divider with harmonics suppression for GSM communications applications is presented. For low-pass filter designing, one open stub, one radial resonator, and two rectangular resonators are used. According to results related to insertion losses (|S21| and |S31|), stopband is wide and equal to 7.5 GHz (3.4-10.9 GHz), under the condition of 20 dB harmonic suppression level. The results show that at the designed frequency of 1.8 GHz, the input return loss (|S11|) and output return losses (|S22| and |S33|) are better than 22 dB, and the isolation between of output ports (|S32|) is better than 30 dB. The size of the proposed power divider is compact and equal to 10.6 × 14.6 mm2. Finally, the proposed power divider was fabricated and the measurement results illustrate a good agreement with simulation results.

Compact four-way suspended-stripline power divider with low loss and high isolation

AbstractA four-way suspended-stripline power divider is presented in this letter. The power dividing network is designed by using the suspended stripline, while the isolation network is designed by using the microstrip line. The vias are used to connect the power dividing network and the isolation network. The even- and odd-mode analysis method is applied to design the presented power divider. The simulated and measured results of the presented power divider show reasonable agreement with each other. The measured input return loss in the band is greater than 28 dB (7.92 to 9.53 GHz), while the measured insertion loss is less than 0.37 dB. The measured output return loss is greater than 20 dB from 7.82 to 9.86 GHz. Besides, the measured output isolation is greater than 20 dB.