Design and Analysis of 2.4 GHz Low-Noise, High-Gain 0.18 μm CMOS Cascode Low-Noise Amplifier for IRNSS Applications

Abstract

Low-Noise Amplifier (LNA) plays a crucial part in Radio Frequency (RF) front-end architecture. This paper mainly focuses on designing LNA for Indian Regional Navigation Satellite System (IRNSS) receiver. IRNSS operates on two frequency bands (L5 and S band) and this design is proposed for S band with the center frequency of 2492.028 MHz. Cascode topologies are considered to be conventional ones and they provide higher gain and better reverse isolation. Four different approaches of single-stage cascode topology, such as Common Source (CS) cascode, Common Gate (CG) cascode, shunt-resistive feedback cascode and current reuse cascode, were designed and their performance metrics, based on gain, Noise Figure (NF), return losses and stability, are presented. Focused on the gain and noise figure improvements, Common Source (CS) cascode with interstage series LC circuit LNA was designed and optimized with input and output matching circuitries. The proposed optimized circuit uses current reuse technique along with CS stage to improve the power gain and to achieve low-noise figure. The interstage LC circuit is mainly implemented to act as a tuning circuit to achieve a narrow range of frequency. The proposed work is simulated using 180 nm CMOS technology Generic Process Design Kit (GPDK) and achieve a power gain (S21) of 24.89, 0.994 dB NF, −16.2 dB input return loss (S11) and −11.06 dB output return loss (S22), with higher reverse isolation around −30.47 dB at 1.8 V power supply.