Organic Board Research Articles

All-Copper Chip-to-Substrate Interconnects Part I. Fabrication and Characterization

A fabrication process has been developed and characterized to create all-copper chip-to-substrate input/output connections. Electroless copper plating followed by low-temperature annealing in a nitrogen environment was used to create an all-copper bond between copper pillars. The ability to fuse the two copper surfaces at modest temperature and pressure is demonstrated. The bond strength for the all-copper structure exceeded after annealing at . During the anneal process, a significant microstructural transformation in the bonded copper–copper interface was observed. The changes were correlated to an increase in the bond strength. The process was characterized with respect to in-plane misalignment of bond sites. Significant planar misalignment, greater than the diameter of the pillars, could be tolerated. Through-plane mismatches between the pillars (pillar gap) as large as could be overcome, resulting in good pillar-to-pillar bonding. Successful silicon-on-silicon and silicon-on-FR-4 bonding was achieved with no degradation of the organic board.

Modified Engelmaier’s model taking account of different stress levels

In this paper, the solder fatigue model created by Werner Engelmaier is modified so that it takes better into account the different stress levels the solder material experiences. This is accomplished by replacing the fatigue ductility constant by a correction term that is temperature- excursion- range-dependent. In order to obtain the correction term, the effect of the temperature cycling profile on lifetime is studied. The correction term obtained is package type specific. More compliant plastic packages with a small coefficient of expansion mismatch with the organic printed wiring board are handled separately, and stiff ceramic packages assembled on an organic board – resulting in a large CTE mismatch – are considered as another entity. Correction terms for both lead-free and tin–lead solder materials are given. This is necessary as the creep characteristics of the solders are different. Comparing solder material specific correction terms makes it possible to determine which solder material performs best in a certain environment and a given assembly type. In the case of ceramic packages, the transition where a eutectic tin–lead solder becomes superior to a SnAgCu solder is expected to take place when temperature excursions are smaller than ca. 70 °C. This indicates that although in a highly accelerated stress test, lead-free solders may be inferior compared to tin–lead solders, in the real field environment, the situation may be reversed.

Using Carrier Fringes to Study the High Temperature Deformation Behavior of a BGA Package Under Extended Dwell Times

There is a compelling need to experimentally understand solder joint deformation behavior at high temperatures over an extended period of time. Accordingly, the deformation behavior of solder joints in a Ceramic Ball Grid Array (CBGA) package mounted on an organic FR4 board under extended dwell time at a high temperature has been studied using laser moire interferometry. The warpage and the in-plane horizontal deformation of the ceramic substrate and the organic board as a function of time were determined. The variation of the normal strains and shear strains in the solder joints with time were also investigated. It was found that increased sensitivity was necessary to accurately determine the strains in the small sized solder joints. A new method utilizing carrier fringes to increase the sensitivity of the moire interferometry system is proposed and has been used to determine the strains in the small sized solder joints. Increased sensitivity can be obtained merely by changing the incident angle of the laser light on the surface of the specimen, thereby making it unnecessary to use expensive phase shifting apparatus with the traditional laser moire system.

Animal Husbandry Practices of Organic Farmers: An Appraisal

In Uttarakhand organic farming is being promoted through a special institution i.e. Uttarakhand Organic Commodity Board (UOCB) through registering the farmers and orienting them towards organic farming. Organic farmers currently practicing and marketing only organic crop products. However, their livestock production practices are also similar to recommended organic standards. Hence, to document their livestock production practices, a total of 180 registered organic farmers selected through multistage sampling technique studied during 2006-07. Cent percent of registered organic farmers were involved in mixed farming enterprises and most of them were with more than one livestock species (farm diversity). The breeds maintained by these farmers were of indigenous and they were raising livestock on the inputs met on farm and from the farms of similar agro-ecological regions. In view of the raising demand for organic livestock products locally as well as internationally, the organic promoting agencies have to focus on orienting these farmers towards stringent organic livestock standards so as to enable them to meet the organic livestock products demand locally as well as internationally.

Filler size and content effects on the composite properties of anisotropic conductive films (ACFs) and reliability of flip chip assembly using ACFs

Flip chip assembly on organic board using anisotropic conductive films (ACFs) is gained more attention because of its many advantages. But to obtain more reliable flip chip assembly, it is necessary to have low coefficient of thermal expansion (CTE) value of ACFs. To control the CTE of ACF materials, non-conductive silica fillers were incorporated into ACFs. The effect of non-conductive silica filler content and size on cure kinetics and thermo-mechanical properties of ACFs was studied. Furthermore, filler content and size effects on reliability of flip chip assembly using ACFs were also investigated. In accordance with increasing filler content, curing peak temperature and storage modulus ( E′) increased. But CTE decreased as the filler content increased. The effect of filler size on composite properties and assembly reliability showed similar tendency with the filler content effect. The smaller filler size was applied, the better composite properties and reliability were obtained. Conclusively, incorporation of non-conductive fillers, particularly in case of smaller size and higher content, in ACFs improves the material properties significantly, and as a result, flip chip assembly using ACFs is resulted in better reliability.

Integrating High-k Ceramic Thin Film Capacitors into Organic Substrates Via Low-Cost Solution Processing

Current organic package-compatible embedded decoupling capacitors are based on thick film (8-16 m) polymer-ceramic composites with dielectric constant (k) of 20-30 and do not have sufficient capacitance density to meet the impedance requirements for emerging high-speed circuits and high power density microprocessors. High-k/high capacitance density ceramics films that can meet the performance targets are generally deposited by high-temperature processing or costly vacuum technology (radio frequency sputtering, PECVD) which are expensive and also incompatible with organic packages. The objective of this project is to develop ultra thin films (100-300nm) with high dielectric constant using organic compatible processes to meet future decoupling applications. In the current study, direct deposition of crystalline ceramic films on organic boards at temperatures less than 100C was demonstrated with the hydrothermal method. Post-hydrothermal treatments were shown to minimize the defects in the as-synthesized hydrothermal barium titanate films and improve the breakdown voltage (BDV) and leakage characteristics. Thin films with high capacitance densities and breakdown voltages of 10V were demonstrated. As an alternate technique, sol-gel technology was also demonstrated to integrate ceramic thin films in organic packages. A major barrier to synthesis of sol-gel films on copper foils is the process incompatibility of the sol-gel barium titanate with the copper electrodes. To enable process compatibility, process variables like sol pyrolysis temperature and time, and sintering conditions/atmosphere were optimized. Capacitance densities above 1.1F/cm was demonstrated on commercial copper foils with a BDV above 10 V. The two technologies reported in this study can potentially meet midfrequency decoupling requirements of digital systems.

Disciplining Microbes in the Implementation of US Federal Organic Standards

The National Organic Standards Board (NOSB), a citizen panel charged with the job of recommending to the US Secretary of Agriculture guidelines for certified organic agriculture, can be analyzed as a ‘boundary organization’. By linking organic farmers' knowledge with peer-reviewed science, the board builds the base of organic agriculture for legitimacy and also develops a new product: federally certified organic agriculture. Examination of organic standards on composting, with a focus on characterizations of composting microbes, reveals the very compromised ability of the NOSB to effect change, however, despite its efforts to build common ground between institutions with very different cultures and historical interests. A focus on discourses of microbes provides insights into the accomplishments of and limits to the influence of the NOSB as well as the larger organic movement. Organizational tactics of the NOSB are best understood within the larger context of institutional commitments to specific forms of agriculture.

Novel Ceramic Composite Substrates for High-Density and High Reliability Packaging

This paper presents the development and evaluation of a large-area carbon-silicon carbide (C-SiC) based composite board material that has the advantages of organic boards in terms of large-area processability and machinability at potentially low-cost while retaining the high stiffness (> 200 GPa) and Si-matched coefficient of thermal expansion (CTE) (~ 2.5 ppm/degC) of ceramics. Test vehicles were fabricated using C-SiC boards for assessing ultra-fine pitch solder joint reliability without underfill as well as the reliability of high-density wiring with microvias on the board. Finite element reliability models were developed to simulate the thermomechanical behavior of test vehicles. From the finite-element simulations as well as accelerated reliability tests, the high stiffness low-CTE C-SiC boards did not show any premature solder joint fatigue failure or dielectric cracking. Furthermore, the C-SiC boards show minimal via-pad misalignment and support the multilayer buildup structure required to achieve very high wiring density. The modeling and experimental results suggest that the low-cost large-area ceramic matrix composite (C-SiC) has superior thermomechanical properties, and is, therefore, a promising candidate substrate material for the emerging microelectronic systems.

Experimental Characterization of Monotonic and Fatigue Delamination of Novel Underfill Materials

No-flow underfill materials reduce assembly processing steps and can potentially be used in fine-pitch flip chip on organic board assemblies. Such no-flow underfills, when filled with nano-scale fillers, can significantly enhance the solder bump reliability, if the underfills do not prematurely delaminate or crack. Therefore, it is necessary to understand the risk of underfill delamination during assembly and during further thermal excursions. In this paper, the interface between silicon nitride (SiN) passivation and a nano-filled underfill (NFU) material is characterized under monotonic as well as thermo-mechanical fatigue loading, and fracture parameters have been obtained from such experimental characterization. The passivation-underfill interfacial delamination propagation under monotonic loading has been studied through a fixtureless residual stress induced decohesion (RSID) test. The propagation of interfacial delamination under thermo-mechanical fatigue loading has been studied using sandwiched assemblies and a model for delamination propagation has been developed. The characterization results obtained from this work can be used to assess the delamination propagation in flip-chip assemblies. Though the methods presented in this paper have been applied to nano-filled, no-flow underfill materials, their application is not limited to such materials or material interfaces.

Tracking “Organic” Agricultural Research in the United States, 1970–1989: What Federal Legislative and Selected USDA-Sponsored Documents Reveal

ABSTRACT This paper enumerates Federal government documentation of the period 1970–1989 pertaining to organic agriculture in the United States, identified in the Congressional Information Service's Cumulative Indices and bibliographies published by the United States National Agricultural Library. These Congressional hearings, Federal legislation, and selected U.S. Department of Agriculture (USDA)-sponsored documents provide an historical context for the 1990 legislation that created the National Organic Program (NOP) and the National Organic Standards Board (NOSB). The paper provides chronological tabulations of the historical documents and discusses the communication difficulties and relationships revealed therein between the Congress, the USDA, and organic producers of the time.

Addressing the Information Needs of Organic Farmers: The Confessions of an ATTRA Specialist

Addressing the Information Needs of Organic Farmers: The Confessions of an ATTRA Specialist

Integrated Hardware and Software for Improved Flatness Measurement With ATC4.1 Flip-Chip Assembly Case Study

Over the past four decades, microelectronic packaging technology has evolved from peripheral, through-hole, and bulk configurations to area-array, surface-mount, and small-profile ones. Among these approaches, flip-chip attachment has become the most favorable choice for its large input/output capabilities and short signal path distributions. Given the prediction that the chip size and power of a single chip package will increase dramatically, substrate warpage of flip-chip packages during assembly and usage has become a major concern. Warpage could cause misalignment between the chip and the substrate, prevent the solder balls from making contact with the substrate flip-chip pads during the reflow soldering process, and induce crack nucleation at the board underfill interface during long-term usage. In this paper, the authors developed an integrated large-area shadow moire system for measuring small and large board and chip package warpage. The hardware is designed to carry out warpage measurement with a resolution on the order of micrometers. Combined with software, the integrated system is fully automated and highly accurate. For the case study, the system is used to characterize the substrate warpage of flip-chip on organic board assemblies. Warpage of substrates at the initial bare-board stage, post-reflow, and post-underfill is measured at room temperatures. It is found that by properly selecting initially warped substrates, post-reflow and post-underfill warpage can be reduced. In addition, warpage measurements at elevated temperatures during thermal cycling and power cycling show that power cycling poses a smaller impact on substrate warpage.

Deformation mechanism and its effect on electrical conductivity of ACF flip chip package under thermal cycling condition: An experimental study

In this study, experimental works are performed to investigate the deformation mechanism and electrical reliability of the anisotropic conductive adhesive film (ACF) joint subjected to temperature cycling for flip chip on organic board (FCOB) assemblies. This paper presents some dominant deformation parameters governing the electrical degradation in an ACF joint between a chip and a substrate when flip chip assembly is heated and cooled. The deformation mechanism of ACF flip chip assemblies during the temperature cycling are investigated using in situ high sensitivity moiré interferometry. A four-point probe method is conducted to measure the real-time contact resistance of ACF joint subjected to the cyclic temperature variation. As the temperature increases below T g of ACF, the bending displacement of assembly decreases linearly. At the temperature higher than T g of ACF, there is no further change in bending behavior and in-plane deformations of a chip and a substrate become approximately free thermal expansion. It is because that soft-rubbery ACF at the temperature above T g cannot provide the mechanical coupling between a chip and a substrate. The effect of bump location on the temperature dependent contact resistance is evident. A characteristic hysteresis in bending curves is observed and discussed. The contact resistance of the corner bumps increases with increasing temperature at a higher rate when compared to that of the middle. Failure analysis is performed to examine the ACF interconnections before and after thermal cycling test. The results indicate that during the thermal loading, the shear deformation is more detrimental to the electrical degradation of ACF joints than normal strain.

Thermal Cycling Reliability and Delamination of Anisotropic Conductive Adhesives Flip Chip on Organic Substrates With Emphasis on the Thermal Deformation

One of the most important issues whether anisotropic conductive film (ACF) interconnection technology is suitable to be used for flip chip on organic board applications is thermal cycling reliability. In this study, thermally induced deformations and warpages of ACF flip chip assemblies as a function of distance from neutral point (DNP) and ACF materials properties were investigated using in situ high sensitivity moire´ interferometry. For a nondestructive failure analysis, scanning acoustic microscopy investigation was performed for tested assemblies. To elucidate the effects of ACF material properties and DNP on the thermal cycling reliability of ACF assembly, Weibull analysis for the lifetime estimation of ACF joint was performed, and compared with thermal deformations of ACF flip chip assembly investigated by moire´ interferometry. Results indicate that the properties of ACF have a significant role in the thermal deformation and reliability performance during thermal cycling testing. Therefore, optimized ACF properties can enhance ACF package reliability during thermal cycling regime.

Warpage-induced lithographic limitations of FR-4 and the need for novel board materials for future microvia and global interconnect needs

The effect of warpage on lithographic capabilities of organic circuit boards with multilayered thin film buildup was investigated. Two to six epoxy layers were built on various candidate boards to characterize the warpage and correlate it with analytical models. Underlying mechanisms were investigated and novel parameters defined to correlate warpage with photodefinition of ultrafine lines and vias on the board. Based on the experiments, warpage specifications for the multifunctional multilayered requirements in a proposed system-on-package (SOP) structure were defined. Experimentally validated FEM models were used to estimate the warpage during the multilayered buildup. Results show that FR-4 is not suitable for future high-density packaging needs and underscore the need for stiffer ceramic-based circuit board materials as replacement for FR-4

Recent Advances in Flip-Chip Underfill: Materials, Process, and Reliability

In order to enhance the reliability of a flip-chip on organic board package, underfill is usually used to redistribute the thermomechanical stress created by the coefficient of thermal expansion (CTE) mismatch between the silicon chip and organic substrate. However, the conventional underfill relies on the capillary flow of the underfill resin and has many disadvantages. In order to overcome these disadvantages, many variations have been invented to improve the flip-chip underfill process. This paper reviews the recent advances in the material design, process development, and reliability issues of flip-chip underfill, especially in no-flow underfill, molded underfill, and wafer-level underfill. The relationship between the materials, process, and reliability in these packages is discussed.

Fundamental Limits of Organic Packages and Boards and the Need for Novel Ceramic Boards for Next Generation Electronic Packaging

The system-on-a-package (SOP) paradigm proposes a package level integration of digital, RF/analog and opto-electronic functions to address future convergent microsystems. Two major components of SOP fabrication are sequential build-up of multiple layers (4–8) of conducting copper patterns with interlayer dielectrics on a board and multiple ICs flip-chip bonded on the top layer. A wide range of passives, wave-guides and other RF and opto-electronic components buried within the dielectric layers provide the multiple functions on a single microminiaturized platform. The routing of future nanoscale ICs with 10,000+ I/Os require multiple build-up layers of ultra fine board feature sizes of 10 μm lines/space widths and 40 μm pad diameters. Current FR4 boards cannot achieve this build-up technology because of dimensional instability during processing. These boards also undergo high warpage during the sequential build-up process which limits the fine-line lithography and also causes misalignment between the vias and their corresponding landing pads. In addition, the CTE mismatch between the silicon die and the board leads to IC-package interconnect reliability concerns, particularly in future fine-pitch assemblies where underfilling becomes complicated and expensive. This work reports experimental and analytical work comparing the performance of organic and novel ceramic boards for SOP requirements. The property requirements as deduced from these results indicate that a high stiffness and tailorable CTE from 2–4 ppm/∘C is required to enable SOP microminiaturized board fabrication and assembly without underfill. A novel ceramic board technology is proposed to address these requirements.

BaTiO3 Films by Low-Temperature Hydrothermal Techniques for Next Generation Packaging Applications

This work reports synthesis, characterization and integration of sub-micron thick nano-grained barium titanate films on organic Printed Wiring Boards (PWB). Barium titanate films were synthesized on titanium foils at 95∘C. SEM of films revealed 80 nm grains. The films were characterized using XRD, FTIR and Raman spectroscopy. As-synthesized films exhibited high capacitance densities and dielectric loss. The films were treated with oxygen plasma to reduce entrapped hydroxyl groups and this resulted in improved dielectric properties. The plasma treated films exhibited a capacitance density of 1 μ F/cm2 and a dielectric loss of 0.06. The high frequency dielectric properties were extracted from s-parameter measurements on CPW structures on these films and were found to be stable up to 8 GHz.

Next Generation of 100-<tex>$murm m$</tex>-Pitch Wafer-Level Packaging and Assembly for Systems-on-Package

According to the latest ITRS roadmap, the pitch of area array packages is expected to decrease to 100 /spl mu/m by 2009. Simultaneously, the electrical performance of these interconnections needs to be improved to support data rates in excess of 10 Gbps, while guaranteeing thermomechanical reliability and lowering the cost. These requirements are challenging, thus, needing innovative interconnection designs and technologies. This paper describes the development of three interconnection schemes for wafer-level packages (WLPs) at 100-/spl mu/m pitch, involving rigid, compliant, and semicompliant interconnection technologies, extending the state of the art in each. Extensive electrical and mechanical modeling was carried out to optimize the geometry of the interconnections with respect to electrical performance and thermomechanical reliability. It was found that the requirements of electrical performance often conflict with those of thermomechanical reliability and the final optimum design is a tradeoff between the two. For the three interconnection schemes proposed, it was found that the electrical requirements can be met fairly well but acceptable mechanical reliability may require organic boards with a coefficient of thermal expansion of 10 ppm/K or lower.

Analysis of Substrates for Single Emitter Laser Diodes

Electrically conductive substrates (i.e., metals) are often used in the mounting of semiconductor laser diodes. While metals offer a good electrical and thermal performance, they restrict the system integration due to lack of signal routing capability. Since the implementations utilizing laser diodes have become more common, the integration level has also become an important factor in these products. Mounting of lasers on insulative substrates is the key to large-scale integration. Organic boards form the de facto standard of insulative substrates; however, their use with lasers is impossible due to low thermal conductivity. Ceramics, however, offer nearly the same thermal performance as metals but as electrically insulative materials also provide the foundation for high integration levels. In this study the effects of three different ceramic substrates on the stresses within diode lasers was evaluated. Finite element method was used to calculate the mounting induced straining and the thermal performance of the substrate. The same procedure was employed to examine the optimum metallization thickness for the ceramic substrates. The results present how greatly the substrate material can affect the very delicate laser diode. The ceramic substrates, though having nearly the same properties, exhibited clearly distinctive behavior and a great difference in thermal and mechanical performance.