On-chip Resistors Research Articles

The NIST Johnson Noise Thermometry System for the Determination of the Boltzmann Constant.

In preparation for the redefinition of the International System of Units (SI), five different electronic measurements of the Boltzmann constant have been performed using different Johnson noise thermometry (JNT) systems over the past seven years. In this paper, we describe in detail the JNT system and uncertainty components associated with the most recent National Institute of Standards and Technology (NIST) determination of the Boltzmann constant: k = 1.380642 9(69) × 10-23 J/K, with a relative standard uncertainty of 5.0 × 10-6 and relative offset of -4.05 × 10-6 from the Committee on Data for Science and Technology (CODATA) 2014 recommended value. We discuss the input circuits and the approach we used to match the frequency response of two noise sources. We present new measurements of the correlated noise of the 4 K on-chip resistors in the quantum-accurate, pseudorandom, voltage-noise source, which we used to estimate the correlated, frequency-dependent, nonthermal noise in our system. Finally, we contrast our system with those used in other measurements and speculate on future improvements.

A CMOS Readout Circuit for Resistive Transducers Based on Algorithmic Resistance and Power Measurement

This paper reports a readout circuit capable of accurately measuring not only the resistance of a resistive transducer, but also the power dissipated in it, which is a critical parameter in thermal flow sensors or thermal-conductivity sensors. A front-end circuit, integrated in a standard CMOS technology, sets the voltage drop across the transducer, and senses the resulting current via an on-chip reference resistor. The voltages across the transducer and the reference resistor are digitized by a time-multiplexed high-resolution analog-to-digital converter (ADC) and post-processed to calculate resistance and power dissipation. To obtain accurate resistance and power readings, a voltage reference and a temperature-compensated reference resistor are required. An accurate voltage reference is constructed algorithmically, without relying on precision analog signal processing, by using the ADC to successively digitize the base–emitter voltages of an on-chip bipolar transistor biased at several different current levels, and then combining the results to obtain the equivalent of a precision curvature-corrected bandgap reference with a temperature coefficient of 18 ppm/°C, which is close to the state-of-the-art. We show that the same ADC readings can be used to determine die temperature, with an absolute inaccuracy of ±0.25 °C (5 samples, min–max) after a 1-point trim. This information is used to compensate for the temperature dependence of the on-chip polysilicon reference resistor, effectively providing a temperature-compensated resistance reference. With this approach, the resistance and power dissipation of a 100 $\Omega $ transducer have been measured with an inaccuracy of less than $\pm 0.55~\Omega $ and ±0.8%, respectively, from −40 °C to 125 °C.

On-Chip Meander Line N-Well Resistor with Shielded Ground Conductor for Q-Factor Improvement

ABSTRACTThe on-chip meander line n-well resistor with a shielded ground conductor inserted parallel between the meander line on the silicon substrate is studied. The new design configuration concept with the shielded ground conductor improved the Q factor compared to those without the shielded ground conductor operating at high frequency. It was confirmed that the design configuration for the shielded ground conductor with a larger coverage area and increasing the number of parallel with the meander signal line was significant in improving the Q-factor performance operating at high frequency. Using this improvement method, the Q-factor value for proposed design meander line n-well structure with shielded ground conductor at 2 µm width in two T shapes has improved around 8% to 9% at 8, 9, and 10 GHz and reduced the parasitic mutual capacitance by 49.35 fF at 10 GHz when compared to the conventional structure of meander line n-well resistors. Shielded ground conductor technique is effective due to reduction of parasitic mutual capacitance. The resulting simulation of the return loss was improved using the shielded ground conductor method, but has poor of insertion loss, due to the skin effect. Overall, it has better performance compared to other designs because it has had significant improvement for Q factor to beyond 4 GHz and better return loss for all the range of frequency.

Analysis of Metal Wire Effect on Temperature Distribution in Stacked IC With Thinned Chip

Temperature distributions and effects of metal wires on thermal properties in stacked 3-D ICs are analyzed with a test structure, which has a top tier chip attached on a bottom dummy chip with adhesive layer. The top tier chips were fabricated by a standard 0.18- $ {\mu }\text{m}$ CMOS process and their thickness ${t} _{{Si}}$ was thinned down to 20 $ {\mu }\text{m}$ . The test structure consists of 24 sensor blocks, each of which has sensor p–n diodes and an on-chip heater resistor, and selector switches. Various kinds of metal wire patterns on the sensor block surface have been examined their thermal effects. The temperature ${T}$ is proportional to the reciprocal of the distance ${L}$ for the single die (SD) device. For the thin ${t} _{ {Si}} {=} 20 {\mu }\text{m}$ stacked device, ${T}$ becomes a logarithmic function. Our thermal simulation results reveal that the heat flow in the thin ${t} _{ {Si}} {=} 20 {\mu }\text{m}$ device becomes 2-D in the chip, whereas the heat flow in the SD device is hemispherical. Although the metal wires decrease ${T}$ in the thinner device, the temperature reduction is relatively small even at the adjacent to the heater in the thin device. The simulation can produce temperature dependence similar to the measured results and consistent with the heat flow models. Metal wire patterns does not affect thermal transient phenomena, though the pulse heating response in the metal wire device without via and contact hole becomes lower due to the less heat transfer from metal wires to Si surface.

PVT-tolerant Current Reference Generation using different PTAT currents

A PVT tolerant precision current reference generator using an all-PTAT approach in 150nm CMOS process is demonstrated. Three different PTAT currents are generated; two from on-chip resistors with different temperature and correlated process coefficients, and the third using Bandgap circuit. Three different sets of process and temperature coefficients allow active cancellation by taking difference of the PTAT currents with the freedom to implement different current manipulation coefficients using ratioed current mirroring as opposed to passive resistor-mixing approaches. The measurement results demonstrate that the reference current achieves a spread of ±5% in its nominal value and a temperature coefficient of 130ppm/°C when measurements are carried out for 21 die-samples along with supply-voltage and temperature variations. The complete design consumes 30uA current to generate 10uA reference current from a 1.8V power supply. The additional circuitry to generate the reference current has a foot-print of 60um × 60um. A supporting mathematical framework is also presented to elaborate the overall behavior of the circuit.

On-Chip Temperature Distribution of Josephson Voltage Standard Devices

A substrate surface temperature characterization for the National Institute of Standards and Technology Josephson voltage standard has been performed by fabricating and measuring Josephson junction arrays with on-chip thermometry. Circuits were designed with a single voltage standard style array consisting of 12 810 junctions. 31 banks of thermometer junctions were placed around the array and microwave termination resistor to monitor temperature via a junction critical current measurement. Temperature rise in devices with on-chip termination resistors were compared to that of devices terminated off-chip. The thermal profiles on several different substrates were measured and compared to determine which substrate exhibited the best thermal transport. Finally, the thermal properties of junctions deposited directly on silicon were compared to those of the junctions deposited on an interface layer. We found that devices with off-chip terminations had half the temperature rise compared to the devices with on-chip termination, and the devices with remotely located terminations exhibited larger constant-voltage steps over a larger frequency/power range than the devices with termination resistors very close to array junctions. Comparing substrates, we found that sapphire was best for transporting heat from voltage standard circuits and that an interface layer did not affect heat transport in the substrate.

Fin-Array Tunneling Trigger With Tunable Hysteresis on (001) Silicon Substrate

We report the fabrication and characterization of a GaAs fin-array tunneling trigger monolithically integrated on an exact (001) silicon substrate. A Schmitt-trigger-like behavior was observed under double sweep condition by connecting the tunnel diode with an on-chip load resistor. The tunneling trigger circuit was studied using load line analysis. Critical parameters of the circuit were extracted. We found that the circuit hysteresis can be tuned by tailoring of the diode dimensions and load resistor values.

Temperature-Stable Piezoelectric MEMS Resonators Using Integrated Ovens and Simple Resistive Feedback Circuits

This paper reports on the design and demonstration of a miniaturized and integrated heater that enables low power ovenization and temperature stability for piezoelectric MEMS resonators. The low power ovenization is implemented by an integrated symmetric oven platform and high thermal-resistance supporting structures. The temperature compensation circuit is formed by a modified Wheatstone bridge with an on-chip dummy resistor and a constant resistance feedback loop is used to stabilize the resonator center frequency over temperature. Through the use of the integrated heater and the simple feedback circuit, we were able to reduce the resonator's intrinsic frequency instability to 100 ppm (from over 2700 ppm) over a temperature range of -35 °C to + 85 °C. Compared with the state of the art, this paper constitutes a fundamental step forward in the demonstration of temperature stable oscillators with a focus on improving resonator temperature stability with very low power consumption. [2016-0182].

A 0.7-V, 8.9- $$\upmu \hbox {A}$$ μ A compact temperature-compensated CMOS subthreshold voltage reference with high reliability

This paper focuses on the study of a compact tem-perature-compensated CMOS voltage reference (VR) with high reliability. The temperature coefficient (TC) of the gate-source voltage for a subthreshold NMOSFET has been derived and utilized to perform effective temperature compensation with a proportional to absolute temperature (PTAT) drain current. The desirable PTAT current is provided with reliable power supply rejection ratio (PSRR) based on low-voltage self-biased cascode subthrehold operation with enhanced negative feedback. The resulting reference voltage is less sensitive to the process variations of on-chip resistors and absolute currents as well as the TC and PSRR. In addition, the impact of the gate-source voltage variation is alleviated, thus ensuring high reliability of the proposed VR. The measurement results without trimming in 40-nm CMOS process demonstrate that the average of TC is 5.1 and 19.1 $$\hbox {ppm}/^\circ \hbox {C}$$ppm/?C in the temperature range of ?20 to ?80 $$^\circ \hbox {C}$$?C and ?40 to ?120 $$^\circ \hbox {C}$$?C, respectively, and the worst PSRR of ?55.0 dB at 300 kHz is achieved, while the line regulation is better than 0.32 mV/V in the supply range of 0.9---1.6 V. The average current consumption is 8.9 $$\upmu \hbox {A}$$μA at 0.7-V supply, with a die area of only 0.006 $$\hbox {mm}^2$$mm2.

A 110 nW Resistive Frequency Locked On-Chip Oscillator with 34.3 ppm/°C Temperature Stability for System-on-Chip Designs

This work presents a sub- $\mu \text {W}$ on-chip oscillator for fully integrated system-on-chip designs. The proposed oscillator introduces a resistive frequency locked loop topology for accurate clock generation. In this topology, a switched-capacitor circuit is controlled by an internal voltage-controlled oscillator (VCO), and the equivalent resistance of this switched-capacitor is matched to a temperature-compensated on-chip resistor using an ultra-low power amplifier. This design yields a temperature-compensated frequency from the internal VCO. The approach eliminates the traditional comparator from the oscillation loop; this comparator typically consumes a significant portion of the total oscillator power and limits temperature stability in conventional RC relaxation oscillators due to its temperature-dependent delay. A test chip is fabricated in $0.18~\mu \text {m}$ CMOS that exhibits a temperature coefficient of 34.3 ppm/°C with long-term stability of less than 7 ppm (12 second integration time) while consuming 110 nW at 70.4 kHz. A radio transmitter circuit that uses the proposed oscillator as a baseband timing source is also presented to demonstrate a system-on-chip design using this oscillator.

A A Integrated Current-Sensing System With % Gain Error and 16 μA Offset From to

This paper presents an integrated current-sensing system (CSS) that is intended for the use in battery-powered devices. It consists of a $10\,\hbox{m}{\Omega} $ on-chip metal shunt resistor, a switched-capacitor (SC) $\Delta \Sigma $ ADC, and a dynamic bandgap reference (BGR) that provides the ADC’s reference voltage and also senses the shunt’s temperature. The CSS is realized in a standard $0.13\,\mu \text{m}$ CMOS process, occupies $1.15\,\text{mm}^2$ and draws $55\,\mu \text{A}$ from a 1.5 V supply. Extensive measurements were made on 24 devices, 12 of which were directly bonded to a printed-circuit board (PCB) and 12 of which were packaged in a standard HVQFN plastic package. For currents ranging from $-5 $ to $+ 5$ A and over a temperature range of $- 55^{\;\circ} {\text{C}}$ to $+ 85^{\;\circ} {\text{C}}$ , they exhibit a maximum offset of $16\;\mu \text{A}$ and a maximum gain error of $\pm 0.3\% $ . This level of accuracy represents a significant improvement on the state of the art, and was achieved by the use of an accurate shunt temperature compensation scheme, a low-leakage sampling scheme, and several dynamic error correction techniques.

A resistive sensing and dual-slope ADC based smart temperature sensor

Modern temperature sensors are applied in industrial electronics where the operating temperature is beyond 150 °C. Existing smart temperature sensors normally support an operating temperature below 125 °C. This paper describes a low-complex high-temperature smart temperature sensor based on resistive ratiometric temperature sensing concept. The sensor elements comprise only two on-chip temperature-dependent resistors. By measuring the ratio of the two resistors, the sensor's actual temperature information is obtained. Especially, non-linear temperature dependent characteristic of the resistor is analyzed and considered in this design. Also, a dual-slope ADC with autozero enabled is developed to determine the ratio of the two resistors and provide the corresponding digital output. The proposed temperature sensor is fabricated in a mature SOI CMOS technology. Experimental results show that a temperature inaccuracy of 2.5 °C can be achieved over a wide temperature range from 25 to 200 °C.

Compact chromium oxide thin film resistors for use in nanoscale quantum circuits

We report on the electrical characterisation of a series of thin amorphous chromium oxide (CrOx) films, grown by dc sputtering, to evaluate their suitability for use as on-chip resistors in nanoelectronics. By increasing the level of oxygen doping, the room-temperature sheet resistance of the CrOx films was varied from 28 Ω/◻ to 32.6 kΩ/◻. The variation in resistance with cooling to 4.2 K in liquid helium was investigated; the sheet resistance at 4.2 K varied with composition from 65 Ω/◻ to above 20 GΩ/◻. All of the films measured displayed linear current–voltage characteristics at all measured temperatures. For on-chip devices for quantum phase-slip measurements using niobium–silicon nanowires, interfaces between niobium–silicon and chromium oxide are required. We also characterised the contact resistance for one CrOx composition at an interface with niobium–silicon. We found that a gold intermediate layer is favourable: the specific contact resistivity of chromium-oxide-to-gold interfaces was 0.14 mΩcm2, much lower than the value for direct CrOx to niobium–silicon contact. We conclude that these chromium oxide films are suitable for use in nanoscale circuits as high-value resistors, with resistivity tunable by oxygen content.

A Signal- and Transient-Current Boosting Amplifier for Large Capacitive Load Applications

A signal- and transient-current boosting (STCB) circuit is proposed and applied to a single-stage amplifier driving large capacitive loads. The proposed STCB circuit provides gain-bandwidth product (GBW) extension, slew-rate (SR) improvement and gain enhancement to the amplifier, with only slight alterations to the frequency response and transient response of the single-stage amplifier driving large capacitive loads. No on-chip capacitor or resistor is required. The STCB amplifier is fabricated in a commercial 0.18-μm CMOS technology. The active chip area is 0.00705 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The supply is 1.8 V, and the current consumption is 20.3 μA. The capacitive load (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O</sub> ) ranges from about 4.4 nF to 19 nF. The measured results with a ~ 19-nF load show the small-signal figure-of-merit (FOMS=GBW·C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O</sub> /power) and the large-signal figure-of-merit (FOML=SR·C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O</sub> /power) are 150345 MHz · pF/mW and 31213 V/μs·pF/mW, respectively, which correspond to improvements of 1.52 times and 1.36 times, respectively, to the prior art. The achieved phase margin and gain margin are 80.8 ° and 36.3 dB, respectively.

A Passive RFID Tag Embedded Temperature Sensor With Improved Process Spreads Immunity for a $-{\hbox {30}}^{\circ}{\hbox {C}}$ to 60$^{\circ}{\hbox {C}}$ Sensing Range

We present an ultra-low power temperature sensor embedded in the passive RFID tag using the TSMC 1P6M 0.18 μm standard CMOS process. Substrate parasitic NPN bipolar pair is exploited to generate the temperature dependent current signals for thermal sensing. A time-domain readout scheme which has high immunity to the on-chip resistor, capacitor and clock frequency process-voltage-temperature (PVT) spreads is further proposed. Measurement results of the embedded sensor within the tag system shows a sensing accuracy of ±1.5 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C (3σ) from -30 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C to 60 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C after one-point calibration at 20 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C, with a sensing resolution of 0.3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C and a sampling rate of 68 samples per second. The embedded sensor draws 0.35 μA from a 1 V supply at room temperature and occupies a chip area of 0.14 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Superconducting-nanowire single-photon-detector linear array

We designed, fabricated, and tested a one-dimensional array of superconducting-nanowire single-photon detectors, integrated with on-chip inductors and resistors. The architecture is suitable for monolithic integration on a single chip operated in a cryogenic environment, and inherits the characteristics of individual superconducting-nanowire single-photon detectors. We demonstrated a working array with four pixels showing position discrimination and a timing jitter of 124 ps. The electronic crosstalk between the pixels in the array was negligible.

Improvement of RRAM Device Performance Through On-Chip Resistors

ABSTRACTResearch in non-volatile memories (NVM) has intensified in the past few years due to the ever increasing demand for information storage and the near ubiquity of handheld electronics. Resistive memory is a leading contender in this NVM market due to its high endurance, random accessibility, scalability and low programming voltage.The addition of an external series resistor or imposing current compliance is often used to limit the current through RRAM devices and to prevent “over-programming” and stuck-at-one (SA1) errors. Here, we demonstrate that utilizing an external series resistor is not efficient in preventing over-programming and an on-chip resistor is more desirable.Poly-silicon bottom electrode based devices (with the poly-silicon electrode acting like an on-chip resistor) and metal bottom electrode devices were fabricated and tested. The presence of the on-chip resistor is shown to enhance the endurance of the RRAM device. This technique of including an on-chip resistor prevents stored current discharge through the device as the device transitions from a high resistance to a low resistance state. A SPICE simulation is also employed to illustrate the benefit of this approach.

Towards the observation of phase-locked Bloch oscillations in arrays of small Josephson junctions

We have designed an experiment and performed extensive simulations and preliminary measurements to identify a set of realistic circuit parameters that should allow the observation of constant-current steps at I=2ef in short arrays of small Josephson junctions under external AC drive of frequency f. Observation of these steps demonstrating phase lock of the Bloch oscillations with the external drive requires a high-impedance environment for the array, which is provided by on-chip resistors close to the junctions. We show that the width and shape of the steps crucially depend on the shape of the drive and the electron temperature in the resistors.

Long hold times in a two-junction electron trap

The hold time τ of a single-electron trap is shown to increase significantly due to suppression of photon assisted tunneling events. Using two rf-tight radiation shields instead of a single one, we demonstrate increase of τ by a factor exceeding 103, up to about 10 h, for a trap with only two superconductor (S)—normal-metal (N) tunnel junctions and an on-chip resistor R ∼ 100 kΩ (R-SNS structure). In the normal state, the improved shielding made it possible to observe τ ∼ 100 s, which is in reasonable agreement with the quantum-leakage-limited level expected for the two-electron cotunneling process.

Quantified Temperature Effect in a CMOS Image Sensor

In recent years, CMOS image sensors (CISs) have increasingly become major players in the solid-state imaging market, a market in which charge-coupled device image sensors were once the dominant product. Exceptional circuit integration capability makes CMOS imagers suitable for implementation in a single-chip imaging system while inducing the temperature variation of an image sensor. In this paper, global and local high-leakage nonuniformities induced by on-chip temperature variations were controlled by both a Peltier junction device and on-chip resistors. Two test chips were fabricated using TSMC 0.13-?m CIS processes and TSMC 1-poly 6-metal 0.18-?m process technology, respectively. As expected, fixed-pattern noise increased with temperature. To quantify the influence of temperature, the maximum depth of an affected region was defined as DAR. The experimental results revealed that the DAR index increased with either an increase in power consumption or a space reduction between the resistor and the pixel array. The DAR index not only characterized affected regions in the experiment but also provided a valuable reference regarding temperature protection for future imager designs.