Analysis of Metal Wire Effect on Temperature Distribution in Stacked IC With Thinned Chip

Abstract

Temperature distributions and effects of metal wires on thermal properties in stacked 3-D ICs are analyzed with a test structure, which has a top tier chip attached on a bottom dummy chip with adhesive layer. The top tier chips were fabricated by a standard 0.18- $ {\mu }\text{m}$ CMOS process and their thickness ${t} _{{Si}}$ was thinned down to 20 $ {\mu }\text{m}$ . The test structure consists of 24 sensor blocks, each of which has sensor p–n diodes and an on-chip heater resistor, and selector switches. Various kinds of metal wire patterns on the sensor block surface have been examined their thermal effects. The temperature ${T}$ is proportional to the reciprocal of the distance ${L}$ for the single die (SD) device. For the thin ${t} _{ {Si}} {=} 20 {\mu }\text{m}$ stacked device, ${T}$ becomes a logarithmic function. Our thermal simulation results reveal that the heat flow in the thin ${t} _{ {Si}} {=} 20 {\mu }\text{m}$ device becomes 2-D in the chip, whereas the heat flow in the SD device is hemispherical. Although the metal wires decrease ${T}$ in the thinner device, the temperature reduction is relatively small even at the adjacent to the heater in the thin device. The simulation can produce temperature dependence similar to the measured results and consistent with the heat flow models. Metal wire patterns does not affect thermal transient phenomena, though the pulse heating response in the metal wire device without via and contact hole becomes lower due to the less heat transfer from metal wires to Si surface.