Quantified Temperature Effect in a CMOS Image Sensor

Abstract

In recent years, CMOS image sensors (CISs) have increasingly become major players in the solid-state imaging market, a market in which charge-coupled device image sensors were once the dominant product. Exceptional circuit integration capability makes CMOS imagers suitable for implementation in a single-chip imaging system while inducing the temperature variation of an image sensor. In this paper, global and local high-leakage nonuniformities induced by on-chip temperature variations were controlled by both a Peltier junction device and on-chip resistors. Two test chips were fabricated using TSMC 0.13-?m CIS processes and TSMC 1-poly 6-metal 0.18-?m process technology, respectively. As expected, fixed-pattern noise increased with temperature. To quantify the influence of temperature, the maximum depth of an affected region was defined as DAR. The experimental results revealed that the DAR index increased with either an increase in power consumption or a space reduction between the resistor and the pixel array. The DAR index not only characterized affected regions in the experiment but also provided a valuable reference regarding temperature protection for future imager designs.