On-chip Interconnects Research Articles

Distant spin entanglement via fast and coherent electron shuttling.

In the quest for large-scale quantum computing, networked quantum computers offer a natural path towards scalability. While recent experiments have demonstrated nearest neighbour entanglement for electron spin qubits in semiconductors, on-chip long-distance entanglement could bring more versatility to connect quantum core units. Here, we employ the moving trapping potential of a surface acoustic wave to realize the controlled and coherent transfer of a pair of entangled electron spins between two distant quantum dots. The subsequent electron displacement induces coherent spin rotations, which drives spin quantum interferences. We observe high-contrast interference as a signature of the preservation of the entanglement all along the displacement procedure, which includes a separation of the two spins by a distance of 6 μm. This work opens the route towards fast on-chip deterministic interconnection of remote quantum bits in semiconductor quantum circuits.

Design and concept proof of an inductive impulse self-destructor in sense-and-react countermeasure against physical attacks

This paper presents an inductive impulse self-destruction circuit utilized in a sense-and-react IC-level countermeasure against physical attacks on a cryptographic processor. Triggered upon an alarm signal assertion by an integrated attack sensor, the proposed circuit instantaneously generates >10 V high-voltage impulse to permanently destruct the cryptographic processor for enhancing tamper resiliency. A compact design with only a single on-chip inductor and a transistor significantly saves the hardware overhead. The inductor accumulates large electric energy in its magnetic field and the switch transistor suddenly opens the accumulated energy to boost the impulse voltage in an inertial manner. Since the inductor is drawn over the cryptographic core by existing on-chip IC interconnections, no extra area for the inductor and no any optional IC process steps are needed. This fully standard CMOS compatible, complete circuit solution, results in no fabrication cost penalty. A prototype implemented in both discrete components and a 0.18 μm standard CMOS process successfully demonstrated the-proof-of-concept.

Marvell ThunderX3: Next-Generation Arm-Based Server Processor

Marvell ThunderX3 is the third-generation Arm-based server processor from Marvell. This article describes the architecture of ThunderX3, going into details of core microarchitecture. ThunderX3 is distinctive among mainstream processors in supporting four SMT threads. The article describes the threading microarchitecture of ThunderX3 and highlights threading benefits. The article also touches on the on-chip interconnect and L3-cache and the power management subsystem. Initial benchmark results from silicon show 30%+ single thread and up to 3X socket level performance gains over the prior generation resulting in industry-leading single thread and socket level performance.

On-chip silicon photonic controllable 2\u2009\xd7\u20092 four-mode waveguide switch

Multimode optical switch is a key component of mode division multiplexing in modern high-speed optical signal processing. In this paper, we introduce for the first time a novel 2 × 2 multimode switch design and demonstrate in the proof-of-concept. The device composes of four Y-multijunctions and 2 × 2 multimode interference coupler using silicon-on-insulator material with four controllable phase shifters. The shifters operate using thermo-optic effects utilizing Ti heaters enabling simultaneous switching of the optical signal between the output ports on four quasi-transverse electric modes with the electric power consumption is in order of 22.5 mW and the switching time is 5.4 µs. The multimode switch exhibits a low insertion loss and a low crosstalk below − 3 dB and − 19 dB, respectively, in 50 nm bandwidth in the third telecom window from 1525 to 1575 nm. With a compact footprint of 10 µm × 960 µm, this device exhibits a relatively large width tolerance of ± 20 nm and a height tolerance of ± 10 nm. Furthermore, the conceptual principle of the proposed multimode switch can be reconfigurable and scalable in multifunctional on-chip mode-division multiplexing optical interconnects.

Analysis and Design of On-Chip RF Interconnect Line for Wideband True-Time Delay Line Application

This paper presents the analytical resistance–capacitance–inductance–conductance (RLCG) model of the on-chip interconnect line (IL) based on its structure, and the proposed model can be used to design IL and analyze the delay characteristics. Using electromagnetic (EM) simulation, the relations between the inductance, quality factor and the width, length of IL are obtained, which verifies the proposed RLCG model of IL. The delay model of IL is derived and verified with respect to the effects of the [Formula: see text] and [Formula: see text] by simulation, which can provide the benefit for the true-time delay line (TTDL) design using IL. This work proposes the experiments on the delay characteristics of 3-bit TTDL with IL based on 0.13[Formula: see text][Formula: see text]m SiGe BiCMOS technology. The group delay and transient delay of the TTDL are measured, which exhibits a maximal relative delay of 35 ps with an average of 5 ps delay resolution over a frequency range of 14–34[Formula: see text]GHz. The results are consistent with the delay analysis based on the proposed IL model.

Structure Fortification of Mixed CNT Bundle Interconnects for Nano Integrated Circuits Using Constraint-Based Particle Swarm Optimization

The emerging VLSI technology and simultaneously highly dense packaging of devices and interconnects in nano-scale chips have prosperously enabled realization of system-on-chip designs and advanced high-performance computing applications. Concurrently, these have aggravated inevitable challenges in miniaturized integrated circuits (ICs). One of the main limiters in the performance of high-speed VLSI designs is the on-chip interconnects. The emerging graphene based mixed carbon nanotube bundle (MCNTB) interconnects have been investigated as one of the most suited and physically realizable on-chip structure. The present work focuses on utilization of MCNTB as nano-interconnects in the optimized way. Determining optimized placement of CNTs in MCNTB configuration is tedious, skilful task and meagerly explored till date. This has been innovatively taken-up in the current work. In the present paper, novel and efficient particle swarm optimization (PSO) technique is explored and innovatively incorporated to obtain optimal distribution of CNTs in a given rectangular area. The objective function considered for the design is to maximize the tube density. Several signal integrity analyses have been executed. The proposed optimized mixed CNT bundle structure is compared with other different configurations of CNT bundle structures. It is analyzed that the proposed optimized MCNTB configuration produces highly favorable results and is apt suitable for futuristic nano IC designs. The different modelling and performance analyses are performed using MATLAB, SPICE and ADS EDA tools.

A survey on pristine and intercalation doped graphene nanoribbon interconnect for future VLSI circuits

The paper presents a review of recent works on pristine and intercalation doped graphene nanoribbon interconnects. Since the last decade, there have been tremendous research interests on graphene-based nanoelectronics. Graphene nanoribbon (GNR) has been projected as an interconnect material to replace the traditional copper interconnects. Since graphene is a planar material, CMOS compatible processes for patterning and making contacts to it, can be developed. Though, fabricating side-contacts in multilayered GNR (MLGNR) is a challenging task, fabrication of top-contact MLGNR is technologically viable. In addition, intercalation doping in top-contact MLGNR improves effective conductivity further. A number of models have been developed to optimize emerging on-chip interconnect technologies and benchmark them against conventional technologies. In this review, physical and electrical models of pristine and intercalation doped MLGNRs have been discussed in brief. A chronological survey towards analytical and spice compatible modeling of pristine and intercalation doped top-contact (TC) and side-contact (SC) MLGNR interconnect, has been presented in this article. A brief review of experimental work on pristine and intercalated GNRs as on-chip interconnect has also been incorporated in this survey. The stability, signal integrity (SI), and power integrity (PI) analysis of pristine and intercalation doped MLGNR interconnect with the presented models have been depicted further. The performance assessments have been compared with conventional copper, and CNT-based interconnects as well. It has been concluded that the side-contact and intercalation doped top-contact MLGNRs can outperform conventional copper-based interconnects.

Signal integrity analysis of bundled carbon nanotubes as futuristic on-chip interconnects

Rigorous technology scaling of integrated circuits to nanometer range aids to acquire prodigious operational speed and versatile functionality in system-on-chip. However, this leads to escalation in interconnect parasitics and non-ideal issues that have become primary bottleneck in the existing copper based on-chip interconnect system. Graphene based carbon nanotube bundle has emerged as prospective interconnect for high speed applications. This paper focuses on bundled carbon nanotubes and their different spatial arrangements viz. single wall CNTs (SWCNTs), multiwall CNTs (MWCNTs) and mixed CNT bundles (MCBs). Such bundle configurations boost the performance of system in terms of reducing system latency and power consumption in addition providing system reliability. The significant novel contribution of this paper lies in executing eye-diagram analysis of the futuristic bundled CNT structures as interconnects. Eye-diagram is an important tool for analysing signal integrity effects. The several performance analyses have been performed in SPICE and ADS EDA tools at 22 nm technology node.

Compact, Highly Efficient, and Controllable Simultaneous 2 × 2 Three-Mode Silicon Photonic Switch in the Continuum Band

Multimode switch (MMS) allows realizing multimode optical communication enabling high-speed communication. However, to develop such an ultrafast switch for simultaneous multimode with a compact size is very challenging. In this paper, we design and demonstrate a compact multimode 2×2 MMS based on numerical simulation methods using silicon Ψ-junctions and multimode interference (MMI) couplers. The switch is controlled by thermal-optic phase shifters which is able to switch simultaneously states of the optical signal between three quasi-transverse electric modes. The MMS exhibits a low insertion loss from -1.5 dB to -3 dB, low crosstalk below -22 dB, and high extinction ratio larger than 22 dB in 40-nm bandwidth in the third telecom window from 1520 to 1560 nm, respectively. With a compact footprint of 12 μm ×1300 μm, the MMS exhibits relatively large dimensional tolerances. Besides, the MMS provides total electric power consumption levels smaller than 103 mW at an ultrafast switching time of 4.4 μs without the impact of the plasmonic effect. Furthermore, the conceptual principle of the proposed MMS can be reconfigurable and scalable in dimensional multifunctional on-chip mode-division multiplexing optical interconnects and promising potential for photonic large scale integration circuits in the continuum band.

DESIGN OF A LOW LATENCY ROUTER FOR ON-CHIP NETWORKS

A problem with long on-chip wires is the resulting delays, and repeater insertion becomes essential to mitigate this problem. Point-to-point wiring leads to an increase in the area and repeater insertion leads to an increase in power consumption. The complexity of System-on-Chip (SoC) designs continues to increase, and traditional bus-based interconnects will not be sufficient to manage the communication requirements of future billion transistor chips. The properties of our OCN are now reviewed. The OCN provides reliable communication. This is achieved by ensuring that data dropping is not allowed. On-Chip Network’s (OCN’s) provide a scalable alternative to existing on-chip interconnects. The key element of the OCN is the router. We present a prototype design of a 5-input, 5-output, scalable router. The router is constructed from a collection of parameterizable and reusable hardware blocks and is a basic building block of the OCN.

WITHDRAWN: Dynamic switching analysis of coupled RLC interconnects with physical and environmental variations

Abstract With continuous downscaling of integrated circuits into deep submicron and nanometer regime, operating at high frequencies, it has become most important to evaluate the reliability and efficiency of on-chip interconnects. The study of device and dynamic variations on dynamic crosstalk in inductive coupled interconnect wires is discussed in this paper. It analyses and studies the effect of driver size, interconnect length, supply voltage and temperature on the coupled interconnect lines. In the analysis, single and cascaded repeaters are used to drive the coupled interconnect lines. For local interconnects, as the driver size increases from 1X to 4X, the propagation delay decreases by 70.9% and the power dissipation increases by 5.75%. For global interconnects, as length of the interconnect increases from 1 mm to 2.5 mm, power dissipation and propagation delay are increased by 56.77% and 51.93% respectively. Analysis of variation of supply voltage and operating temperature is also carried out in this work. The analysis is carried out using geometric dimensions and the impedance parameters of copper interconnect extracted from PTM models for 45 nm CMOS technology node.

Ultrafast reconfigurable nanoscale optical switch based on photonic crystal waveguide

We propose reconfigurable photonic switches with very low input power, ultracompact size, fast response, and low optical loss for high-speed optical network and on-chip interconnect applications. The photonic crystal waveguide-based nanostructure is used to realize the reconfigurable 3 × 3 and 4 × 4 optical switches. The two different operating wavelengths of 1550 and 1630 nm play a significant role in the nanophotonic switching platform. The reconfiguration of optical signal path is effectively attained using these wavelengths with low delay time and high data rate. The performance of nanoswitch parameters is numerically investigated by the finite-difference time-domain method. The proposed optical switch is designed with a low input power of 0.5 mW, fast response time of 607.33 fs, and high data rate of 1.646 Tbps. This high-performance device can be suitable for lightwave communication network, quantum computing, and nanoscale photonic integrated systems.

On the routing and scalability of MZI-based optical Beneš interconnects

Silicon Photonic interconnects are a promising technology for scaling computing systems into the exa-scale domain. However, there exist significant challenges in terms of optical losses and complexity. In this work, we evaluate the applicability of a thermally/electrically tuned Beneš network based on Mach–Zehnder Interferometers for on-chip and inter-chip interconnects as regards its scalability. We examine how insertion loss, laser power and switching energy consumption scale with the number of endpoints. In addition, we propose a set of hardware-inspired routing strategies that leverage the inherent asymmetry present in the switching components. We evaluate a range of network sizes, from 16 up to 256 endpoints, using 8 realistic and synthetic workloads and found very promising results. Our routing strategies offer a reduction in path-dependent insertion loss of up to 35% in the best case, as well as a laser power reduction of 31% for 32 endpoints. In addition, bit-switching energy is reduced by between 8% and 15% using the most efficient routing strategy, depending on the communication workload. We also show that workload execution time can be reduced with the best strategies by 5%–25% in some workloads, while the worst-case increases are at most 3%. Using our routing strategies, we show that under the examined technology parameters, a 32-endpoint interconnect can be considered for the NoC domain in terms of insertion loss and laser power, even when using conservative parameters for the modulator.

Traffic aware routing in 3D NoC using interleaved asymmetric edge routers

Network-on-Chip (NoC) has emerged as a cost-effective on-chip interconnects solution for Tiled Chip Multi Processors (TCMP) where many computational cores occupy a single chip. The performance of NoC network can be greatly enhanced by incorporating 3D IC technology formed by stacking several active NoC layers using Through Silicon Via (TSV) vertical interconnections. 3D NoC routers improve network throughput and have minimal latency at the cost of increased router area and power dissipation. Performance degradation can occur in 3D structures due to unequal traffic distribution across the chip leading to larger power density and larger on-chip temperature that affect system reliability. In this paper, we come up with an interleaved vertical edge routing design approach in 3D NoC that employs asymmetrical routing algorithm and uses a unique flit prioritization unit for improving performance of bufferless mesh NoC. Experimental results indicate that our proposed router has better network performance with minimal hardware overhead when compared with conventional bufferless networks, engaging same number of routers.

Drift-diffusion simulation of photodetector with controlled relocation of carrier density peaks

A photodetector with controlled relocation of carrier density peaks is a promising optoelectronic device designed for the operation as a part of on-chip optical interconnections together with a high-speed laser-modulator. Previously, we estimated the back-edge performance of the sensor using a combined quantum-mechanical model that had not taken into account certain physical aspects of charge carrier transport in the device structure. In this paper, we propose a two-dimensional drift-diffusion model allowing for the comprehensive analysis of transients in the photodetector with controlled relocation within the semiclassical approach. To implement the model, we develop a technique of finite difference numerical simulation and applied software. The obtained simulation results enable us to clarify the operation mode and connection principle of the photodetector with controlled relocation and to improve its performance through the formation of special carrier-holding layers.

WITHDRAWN: Impact of device and dynamic variations on functional crosstalk noise and delay in inductively coupled interconnects

With continuous downscaling of integrated circuits into deep submicron and nanometer regime, operating at high frequencies, it has become most important to evaluate the reliability and efficiency of on-chip interconnects. The study of device and dynamic variations on functional crosstalk in inductive coupled interconnect wires is discussed in this paper. It analyses and studies the effect of driver size and temperature on the coupled interconnect lines. In the analysis, single and cascaded repeaters are used to drive the coupled interconnect lines. The study reveals that the maximum positive forward crosstalk noise of the cascaded repeater driven interconnect is 33.61 percent smaller than the peak positive forward crosstalk noise of minimum sized single repeater driven interconnect. The variation in supply voltage and temperature impacts the propagation delay and power dissipation of coupled interconnects. It is observed that the propagation delay decreases, and power dissipation increases with increase in supply voltage. It is also evaluated that the propagation delay of the coupled interconnect increases with increase in temperature for the combined range of commercial and military applications ranging from −55 °C to 125 °C. The analysis is carried out using geometric dimensions and the impedance parameters of copper interconnect extracted from PTM models for 45 nm CMOS technology node.

Ultrathin Single‐Crystalline 2D Perovskite Photoconductor for High‐Performance Narrowband and Wide Linear Dynamic Range Photodetection

For next-generation Internet-of-Everything applications, for example, artificial-neural-network image sensors, artificial retina, visible light communication, on-chip light interconnection, and flexible devices, etc., high-performance microscale photodetectors are in urgent demands. 2D material (2DM) photodetectors have been researched and demonstrated impressive performances. However, they have not met the demands in filterless narrowband photoresponse, wide linear dynamic range (LDR), ultralow dark current, and large on/off ratio, which are key performances for these applications. 2D Ruddlesden-Popper perovskites (2D-RPPs) are recently highlighted photovoltaic and optoelectronic materials. Embedding ultrathin 2D-RPPs into 2DM photodetectors holds potentials to improve these performances. Herein, a single-crystalline ultrathin (PEA)2 PbI4 is integrated into a vertical-stacked graphene-(PEA)2 PbI4 -graphene micro photoconductor (V-PEPI-PC). V-PEPI-PC exhibits narrowband photoresponses at 517nm with a full-width-at-half-maximum of 15nm and a wide LDR of 122dB. Due to the multiple quantum wells in (PEA)2 PbI4 , V-PEPI-PC demonstrates an ultralow dark current of 1.1 × 10-14 A (44 pA mm-2 ), a high specific detectivity of 1.2 × 1013 Jones, and a high on/off ratio of 1.6 × 106 . Owing to the short vertical channel, V-PEPI-PC shows a fast response rise time of 486 µs. Therefore, the vertical-stacked photodetectors based on hybrid 2D-RPPs and 2DMs may have great potentials in future optoelectronics.

(Electrodeposition Division Research Award Address) Superconformal Deposition: Where We Are and Where We Might Go

Superconformal deposition processes for void-free filling of features have developed remarkably over the first two decades of this century. Superconformal copper deposition, aka “superfill”, enabled void-free copper filling of features with conductive surfaces having aspect ratios unimaginable when implemented in on-chip interconnects in 1997. The only known mechanism, already more than 40 years old, provided only more modest superconformal feature filling through a gradient of deposition rate that scaled with a gradient of suppressor concentration arising from incorporation in the depositing metal. A new mechanism, for the copper “superfill”, was determined in 2001: local coverage of a strongly bound but surfactant accelerator arose through area change that accompanied deposition on nonplanar surfaces. Copper “superfill” through this Curvature Enhanced Accelerator Coverage, or CEAC, mechanism accompanied and accounted for the decrease of feature size in on-chip interconnects over the next ten years. Along the way the CEAC mechanism was shown to be generic to the coinage metals of silver and gold. In all cases, feature filling was shown to be predicted a priori by CEAC-based models using only kinetics derived from studies on planar substrates.In the meantime, the microelectronics industry began to pursue wafer stacking that hinged upon void-free copper filling of much larger Through Silicon Vias, TSV, for which the CEAC mechanism was poorly suited. Demonstrations of bottom-up copper filling incompatible in both geometry and additive-chemistry with the CEAC mechanism required a new mechanistic understanding. In 2012 the old, linear model for suppressor containing electrolytes was replaced by a model reflecting suppressors whose deactivation was so non-linear in potential and concentration that suppression breakdown yielded increasing negative current with increasing positive potential during cyclic voltammetry. Models based on this S-shaped negative differential resistance (S-NDR) predicted the extreme bottom-up nature of the copper filling. Subsequent years brought demonstrations of generality with gold, nickel, cobalt, zinc and copper, albeit manifesting in two very different filling geometries: activation of only the bottom-up surface and activation of the bottom surface with a portion of the adjacent sidewalls. Filling of features having much larger dimensions as well as geometries such as through holes was also demonstrated. In all cases, the filling evolution was shown to be a-priori predictable by S-NDR based models using only kinetics derived from studies on planar substrates.Today we find ourselves with the next superconformal filling process requiring new mechanistic understanding. Gold filling exhibits the bottom-up geometry of suppressor-derived S-NDR filling but with a bismuth additive that accelerates as in CEAC filling. It is thereby explained by neither. Void-free, bottom-up filling has been achieved in trenches whose depths range from a few micrometers to a quarter of a millimeter. Trenches with aspect ratios as low as unity and as high as fifty-six (!) have been successfully bottom-up filled, and surface profiles indicate the limit has not been reached. Adsorption and deposition exhibit a unique nonlinear dependence on transport, and bottom-up filling halts automatically at a depth within patterned features defined by potential that, equivalently, yields a tell-tale potential signature upon filling under galvanodynamic control. Uniformity of filling is excellent across patterned substrates. The new process satisfies a need outside the area of microelectronics: gold filling of trenches in x-ray diffraction gratings. As in the past, understanding will enable superconformal electrodeposition to meet the evolving needs of a new technology. Figure 1

Squeezing of intensity noise in nanolasers and nanoLEDs with extreme dielectric confinement

Low-noise light sources are important for on-chip interconnects, sensors, and quantum technology. We show that, using novel cavity designs featuring deep sub-wavelength confinement, it is possible to strongly reduce quantum fluctuations over a large bandwidth. The results could enable integrated sources with extremely low amplitude noise.

Token ring arbitration scheme for on-chip CDMA bus architectures

CDMA based on-chip interconnects have recently drawn attention due to lower variance of data transfer latency compared with the shared-bus. In this paper, we present a novel design of CDMA bus arbitration unit, which allocates codewords to system nodes and resolves destination conflicts, that is, ensures that at any time all parallel transmissions are destined to different nodes. The arbitration unit is characterized by a distributed architecture in the form of a ring composed of multiple simple ring elements, each of which is attached to one system node. In comparison with conventional centralized arbiter designs, the proposed solution improves the scalability of the CDMA bus-based multi-core SoCs, enables CDMA bus to operate at higher frequencies, and allows the implementation of more elaborated arbitration algorithms, adapted to various CDMA bus variants, with low hardware complexity. Simulation results show that the proposed distributed arbitration unit represents an efficient solution for achieving high throughput and low latency data transmission in CDMA bus-based SoCs.