DESIGN OF A LOW LATENCY ROUTER FOR ON-CHIP NETWORKS

Abstract

A problem with long on-chip wires is the resulting delays, and repeater insertion becomes essential to mitigate this problem. Point-to-point wiring leads to an increase in the area and repeater insertion leads to an increase in power consumption. The complexity of System-on-Chip (SoC) designs continues to increase, and traditional bus-based interconnects will not be sufficient to manage the communication requirements of future billion transistor chips. The properties of our OCN are now reviewed. The OCN provides reliable communication. This is achieved by ensuring that data dropping is not allowed. On-Chip Network’s (OCN’s) provide a scalable alternative to existing on-chip interconnects. The key element of the OCN is the router. We present a prototype design of a 5-input, 5-output, scalable router. The router is constructed from a collection of parameterizable and reusable hardware blocks and is a basic building block of the OCN.