Design of a guaranteed throughput router for on-chip networks

Abstract

The complexity of system-on-chip (SoC) designs continues to increase, and traditional bus-based interconnects will not be sufficient to manage the communication requirements of future billion transistor chips. On-chip networks (OCNs) provide a scalable alternative to existing on-chip interconnects. The key element of the OCN is the router We present a prototype design of a 5-input, 5-output, scalable guaranteed throughput (GT) router The router is constructed from a collection of parameterizable and reusable hardware blocks and is a basic building block of the OCN. The router supports wormhole routing, and is characterized by an area of 0.1 mm/sup 2/ in 0.18 micron CMOS technology.