A generic CAD tool for efficient NoC design

Abstract

Network on chip (NoC) using packet switching is a solution to cope with complex system on chip (SoC) communications. However, tools are needed to help designers to deal with NoC. The two elements composing an NoC are its routers and its network interfaces (NI). We focus on the specification and generation steps of the /spl mu/spider NOC design flow that addresses what we consider as the main features of a realistic and useful NoC. Firstly, the synthesis tool is based on a generic router through a user friendly design interface. Secondly, it supports the management of different levels of quality of service (QoS), allowing a guaranteed throughput (GT) service in addition to a classical best effort (BE) service. Finally, it can be tuned to handle asynchronous communications. The paper presents the router architecture and its various custom characteristics. We show the tradeoff between a hierarchical QoS channel implementation and the performance of the system.