Traffic aware routing in 3D NoC using interleaved asymmetric edge routers

Abstract

Network-on-Chip (NoC) has emerged as a cost-effective on-chip interconnects solution for Tiled Chip Multi Processors (TCMP) where many computational cores occupy a single chip. The performance of NoC network can be greatly enhanced by incorporating 3D IC technology formed by stacking several active NoC layers using Through Silicon Via (TSV) vertical interconnections. 3D NoC routers improve network throughput and have minimal latency at the cost of increased router area and power dissipation. Performance degradation can occur in 3D structures due to unequal traffic distribution across the chip leading to larger power density and larger on-chip temperature that affect system reliability. In this paper, we come up with an interleaved vertical edge routing design approach in 3D NoC that employs asymmetrical routing algorithm and uses a unique flit prioritization unit for improving performance of bufferless mesh NoC. Experimental results indicate that our proposed router has better network performance with minimal hardware overhead when compared with conventional bufferless networks, engaging same number of routers.